Mitsubishi Electric Corporation

Kohei Ebihara

Shiro Hino

Hiroshi Watanabe

Kenji Hamada

Akihiro Koyama

Akihiko Furukawa

Naruhisa Miura

Tsuyoshi Kawakami

Koji Sadamatsu

Kotaro Kawahara

Masayuki Furuhashi

Kazuyuki Sugahara

Masayuki Imaizumi

Takanori Tanaka

Yasuhiro Kagawa

Yutaka Fukui

Yoshiyuki Nakaki

Shuhei Nakata

Rina Tanaka

Kazuya Konishi

Yoshio Fujii

Hideyuki Hatta

Kensuke Taguchi

Yuichi Nagahisa

Takaaki Tominaga

Yukiyasu Nakao

Yasushi Takaki

Hidenori Koketsu

Koji Okuno

Yuji Murakami

Yusuke Yamashiro

Kosuke Miyazaki

Masanao Ito

Naruto Miyakawa

Akemi Nagae

A semiconductor device includes: a semiconductor substrate having a drift layer of a first conductivity type; an active region in which a main current flows in a thickness direction of the semiconductor substrate; a terminal region of a second conductivity type formed in a surface layer of the drift layer and surrounding the active region; a covering material covering the terminal region; and a peripheral well region of a first conductivity type formed in the surface layer of the drift layer on an outer side of the terminal region and having an impurity concentration higher than that of the drift layer, wherein a peripheral end of the covering material is arranged on an inner side of a peripheral end of the semiconductor substrate, and the peripheral well region is at least partially formed under the covering material and not formed under a peripheral end of the covering material.

Semiconductor device, electric power conversion device, and method for manufacturing semiconductor device

In a semiconductor device, a semiconductor substrate is divided into an inner region in which an active region is provided and an outer region surrounding the inner region. The semiconductor device includes a semiconductor layer of a first conductivity type, a termination well region of a second conductivity type selectively provided in an upper layer portion of the semiconductor layer to surround the inner region, an impurity region selectively provided in an upper layer portion of the termination well region, a front surface electrode, a back surface electrode, an insulation film being provided to partially cover a top of the termination well region, an outer peripheral wire layer surrounding the inner region, at least a part of which is provided on the insulation film, and an interlayer insulation film at least covering the insulation film and the outer peripheral wire layer.

Semiconductor device and power conversion device

To mitigate adverse effects on a surface electrode of a semiconductor device. The semiconductor device includes: a first well region formed in a surface layer of an upper surface of a drift layer; a gate electrode; a second well region surrounding the first well region as seen in plan view; and a gate portion covering an interlayer insulation film and the gate electrode exposed from the interlayer insulation film. An outside edge portion of the gate electrode is farther from the first well region than an outside edge portion of the gate portion and closer to the first well region than an outside edge portion of the second well region.

A semiconductor device includes a semiconductor layer including a super junction layer in which an n-type pillar layer and a p-type pillar layer are alternately disposed and a p-type withstand voltage holding structure formed on an upper layer part of the semiconductor layer to surround an active region. At least one withstand voltage holding structure overlaps with the super junction layer in a plan view. At least one withstand voltage holding structure overlapping with the super junction layer in a plan view has a gap which is an intermittent part of the withstand voltage holding structure.

Semiconductor device, power conversion device and method of manufacturing semiconductor device

An SBD includes: a terminal well region formed to surround an active region; a field insulating film formed to cover part of the terminal well region; a surface electrode formed on a drift layer on an inner side in relation to the field insulating film and electrically connected to the terminal well region; a surface protection film covering an end portion on an outer side of the surface electrode; and a back surface electrode formed on a back surface of a single crystal substrate. An end portion of an outer side of the surface electrode in the corner portion of the terminal region is located on an inner side in relation to the end portion of the outer side of the surface electrode in a straight portion of a terminal region based on a position of an end portion of an outer side of the terminal well region.

The present invention relates to a semiconductor device, wherein the semiconductor substrate includes: a semiconductor layer; and a well region, the semiconductor device includes: a surface electrode provided on a second main surface on a side opposite to a first main surface; a back surface electrode provided on the first main surface; and an upper surface film covering an end edge portion of the surface electrode and at least part of an outer side region outside an end surface of the surface electrode of the semiconductor substrate, the well region includes a portion extending to the outer side region and a portion extending to an inner side region inside the end surface of the surface electrode, and the upper surface film includes at least one outer peripheral opening part provided along an outer periphery of the surface electrode away from the surface electrode of the outer side region.

A semiconductor substrate has a first surface and a second surface that includes an inner region and an outer region. The semiconductor substrate includes a drift layer of a first conductivity type and a terminal well region of a second conductivity type. The terminal well region includes a portion that extends from between the inner region and the outer region toward the outer region. A first electrode is on the first surface. A second electrode is on at least part of the inner region and electrically connected to the terminal well region, and has its edge located on a boundary between the inner region and the outer region. A peripheral structure is provided on part of the outer region, away from the second electrode. A surface protective film covers the edge of the second electrode and at least part of the outer region and has the peripheral structure engaged therein.

Semiconductor device and power converter

A technique is provided for effectively suppressing a forward voltage shift due to occurrence of a stacking fault. A semiconductor device relating to the present technique includes a first well region of a second conductivity type, a second well region of the second conductivity type which is so provided as to sandwich the whole of a plurality of first well regions in a plan view and has an area larger than that of each of the first well regions, a third well region of the second conductivity type which is so provided as to sandwich the second well region in a plan view and has an area larger than that of the second well region, and a dividing region of a first conductivity type provided between the second well region and the third well region, having an upper surface which is in contact with an insulator.

Semiconductor device

An object of the present invention is to provide a highly reliable semiconductor device by preventing precipitation of an oxide to prevent peeling of a resin layer. The semiconductor device includes: a resin layer provided so that at least a part of the resin layer extends on a front surface of a semiconductor layer on an outer peripheral side with respect to an outer peripheral end of a field insulating film; and a floating well region spaced apart from a termination well region in a surface layer of the semiconductor layer, the floating well region formed to be in contact with an outer peripheral end of the field insulating film to extend to the outer peripheral side with respect to the outer peripheral end of the field insulating film.

Semiconductor device and power conversion apparatus

In a termination region of a SiC-MOSFET, suppressing operation of a p-n diode between a well and a drift layer sometimes decreases reliability during high-speed switching. In a termination region of a SiC-MOSFET with a built-in SBD are provided second well region having an impurity concentration lower than the impurity concentration in a well region in an active region, and a high-concentration region that is formed on a surface layer of the second well region, has an impurity concentration higher than the impurity concentration in the well region in the active region, and is ohmic-connected to a source electrode.

Silicon carbide semiconductor device and power conversion device

A semiconductor device includes an n-type drift layer formed on a semiconductor substrate having an off-angle, plurality of p-type pillar regions formed in the drift layer, and a surface electrode formed on the drift layer including the plurality of p-type pillar regions. A plurality of withstand voltage holding structures which are p-type semiconductor regions are formed in a surface layer of the drift layer including the plurality of p-type pillar regions to surround an active region. Each of the plurality of p-type pillar regions has a linear shape extending in a direction of the off-angle of the semiconductor substrate. Each of the plurality of withstand voltage holding structures has a frame-like shape including sides extending in parallel with the plurality of p-type pillar regions and sides perpendicular to the plurality of p-type pillar regions in a planar view.

Supposing x is defined as a position of an end of a depletion layer extending when a rated voltage V [V] is applied to a rear surface electrode, Wis defined as a distance between the position x and an outer peripheral edge of a surface electrode in an outer peripheral direction, Wis defined as a distance between the position x and an outer peripheral edge of a field insulating film in the outer peripheral direction, t [&#x3bc;m] is defined as a film thickness t [&#x3bc;m] of the field insulating film, a layout of a terminal part is defined so that an electrical field in the field insulating film at the position x expressed as WV/t(W+W) is 3 MV/cm or smaller.

Semiconductor device with a well region

A semiconductor layer having n-type is made of silicon carbide, and has an element region and a terminal region. A plurality of field limiting ring regions having p-type are provided in the terminal region of the semiconductor layer, and are arranged spaced apart from one another. A field insulating film is provided in the terminal region of the semiconductor layer, and is in contact with the field limiting ring regions and the semiconductor layer. Each of the field limiting regions includes a halogen-containing field limiting ring part in contact with the field insulating film and containing halogen family atoms.

Silicon carbide semiconductor device having halogen field limiting ring regions and method of manufacturing same

A semiconductor device includes: a plurality of semiconductor switching elements that are a plurality of MOSFETs each including a Schottky barrier diode; a first ohmic electrode disposed above a first region of a well region and electrically connected to the first region, the first region being on the opposite side from a predefined region; a first Schottky electrode disposed on a semiconductor layer exposed at the first region of the well region; and a line electrically connected to the first ohmic electrode, the first Schottky electrode, and a source electrode. The device enables reduction of a breakdown in a gate insulating film.

An object of the present invention is to provide a semiconductor device capable of satisfactorily securing a breakdown voltage not only in a cell region but also in an edge termination region in a super junction structure. A semiconductor device according to the present invention includes a drift region of a first conductivity type and a pillar region of a second conductivity type a RESURF layer formed across a plurality of the pillar regions in an edge termination region and extending in the thickness direction from surfaces of the drift region and the pillar region, and a high-concentration region of the second conductivity type formed in a surface of the RESURF layer, the high-concentration region being higher in impurity concentration than the RESURF layer, no pillar region being formed under the high-concentration region in the thickness direction.

Growing community of inventors

Tokyo, Japan

Kohei Ebihara