Mitsubishi Electric Corporation

Fuji Electric Co., Ltd.

National Institute of Advanced Industrial Science and Technology

Kohei Adachi

Yutaka Fukui

Katsutoshi Sugawara

Rina Tanaka

Kazuya Konishi

Hideyuki Hatta

Shiro Hino

Manabu Takei

Kazuhiro Mochizuki

Yoshiyuki Yonezawa

Ryoji Kosugi

A silicon carbide semiconductor device includes: a body region of a second conductivity type provided on a drift layer of a first conductivity type; a source region of a first conductivity type provided on the body region; a source electrode connected to the source region; a gate insulating film provided on an inner surface of a trench; a gate electrode provided inside the trench with interposition of the gate insulating film; a protective layer of a second conductivity type provided below the gate insulating film; a connection layer of a second conductivity type being in contact with the protective layer and the body region; and an electric field relaxation layer of a second conductivity type being in contact with a bottom surface of the connection layer, provided below the connection layer, and having a lower impurity concentration of a second conductivity type than the connection layer.

Silicon carbide semiconductor device, power conversion apparatus, and method for manufacturing silicon carbide semiconductor device

A drift layer is formed of silicon carbide and has a first conductivity type. A trench bottom protective layer is provided on a bottom portion of a gate trench and has a second conductivity type. A depletion suppressing layer is provided between a side surface of the gate trench and the drift layer, extends from a lower portion of a body region up to a position deeper than the bottom portion of the gate trench, has the first conductivity type, and has an impurity concentration of the first conductivity type higher than that of the drift layer. The impurity concentration of the first conductivity type of the depletion suppressing layer is reduced as the distance from the side surface of the gate trench becomes larger.

Silicon carbide semiconductor device, power converter, method of manufacturing silicon carbide semiconductor device, and method of manufacturing power converter

A silicon carbide semiconductor device includes a diffusion protective layer provided below a gate insulating film, a gate line provided on an insulation film on the bottom face of a terminal trench and electrically connected to a gate electrode, the terminal trench being located more toward the outer side than the gate trench, a gate pad joined to the gate line in the terminal trench, a terminal protective layer provided below the insulation film on the bottom face of the terminal trench, and a source electrode electrically connected to a source region, the diffusion protective layer, and the terminal protective layer. The diffusion protective layer has first extensions that extend toward the terminal protective layer and that are separated from the terminal protective layer. This configuration inhibits an excessive electric field from being applied to the gate insulating film provided on the bottom face of the gate trench.

Semiconductor device and power converter

A semiconductor device that includes a SiC semiconductor substrate; a SiC epitaxial layer having an impurity concentration lower than that of the SiC semiconductor substrate; a first semiconductor layer including first semiconductor pillars and second semiconductor pillars; a second semiconductor layer; a device active region; a termination region; a channel stopper region having an impurity concentration higher than that of the SiC epitaxial layer; and a plurality of first chip end portions and a plurality of second chip end portions, and a surface of the first side surface is covered with an impurity region having an impurity concentration higher than those of the first semiconductor pillar and the SiC epitaxial layer and is connected to the channel stopper region.

Semiconductor device

A semiconductor device including: a trench gate; a trench-bottom protecting layer of a second conductivity type provided in a semiconductor layer of a first conductivity type while contacting a bottom of trenches; and a depletion suppressing layer of the first conductivity type provided between adjacent trench-bottom protecting layers, wherein the depletion suppressing layer includes an intermediate point that is horizontally equidistant to the adjacent trench-bottom protecting layers and is formed of a size to contact neither the trenches nor the trench-bottom protecting layers, and an impurity concentration of the depletion suppressing layer is set higher than an impurity concentration of the semiconductor layer.

Semiconductor device and power conversion device

A gate connection layer () includes a portion placed on an outer trench (TO) with a gate insulating film () being interposed. A first main electrode () includes a main contact (CS) electrically connected to a well region () and a first impurity region () within an active region (), and an outer contact (CO) being spaced away from the active region () and in contact with a bottom face of the outer trench (TO). A trench-bottom field relaxing region () is provided in a drift layer (). A trench-bottom high-concentration region () has an impurity concentration higher than that of the trench-bottom field relaxing region (), is provided on the trench-bottom field relaxing region (), and extends from a position where it faces the gate connection layer () with the gate insulating film () being interposed, to a position where it is in contact with the outer contact (CO) of the first main electrode ().

A semiconductor device in which an interlayer insulation film covers striped gate electrodes with a thickness larger than a thickness of a gate oxide film. The interlayer insulation film includes first contact holes outside each striped trench, and second contact holes inside the striped trench. In a plan view, striped active regions and striped contact regions both extending in a longitudinal direction exist. The striped active regions and the striped contact regions are alternately and repeatedly disposed in a direction perpendicular to the longitudinal direction. In each of the striped active regions, the source electrode is connected to a source region through the first contact hole. In each of the striped contact regions, the source electrode is connected to a protective diffusion layer through the second contact hole.

Growing community of inventors

Tokyo, Japan

Kohei Adachi