Parade Technologies, Ltd.

Lattice Semiconductor Corporation

Octillion Communications, Inc.

Kochung Lee

Ming Qu

Hongquan Wang

Quan Yu

Yuntao Zhu

Zhengyu Yuan

Ji Zhao

Liang Chang

Liang Xu

Edwin Chan

Yuanping Chen

Lei Xie

Min She

Xiang Zhu

Shengyuan Zhang

Xueping Jiang

Qing Chen

YiTing Chen

Cindy Cheng

An electronic device (e.g., a CTLE circuit of a receiver of a data link) includes a current source and two differential transistor groups. The current source is configured to generate a bias current according to a data rate of data carried by a pair of differential input signals. A subset of the two differential transistor groups is configured to be driven by the bias current to generate a pair of differential output signals from the pair of differential input signals. The two differential transistor groups include a first plurality of transistors receiving a first input signal and a second plurality of transistors receiving a second input signal. The first and second input signals form the pair of differential input signals. In some implementations, each transistor is coupled to a biasing circuit including a DC path coupled to an adjustable biasing voltage level for selecting and deselecting the respective transistor.

Continuous time linear equalizers (CTLEs) of data interfaces

This application is directed to a data interface having an input interface for receiving a differential input signal and a reference interface for providing a predefined reference voltage. A high pass filter is coupled to the input interface, and configured to filter the differential input signal and generate a filtered differential input signal. A differential integrator is coupled to the high pass filter and reference interface, and configured to receive the filtered differential input signal and generate a differential output signal including a first output signal and a second output signal. Each of the first and second output signals has a common mode output voltage substantially equal to the predefined reference voltage. In some embodiments, the data interface includes a connector including a plurality of data lanes and a pair of command pins that are distinct from the data lanes and coupled to the input interface.

Receiver circuit with automatic DC offset cancellation in display port applications

This application is directed to frequency controlling in an electronic device that includes a selector, a clock generated, and a controller. The selector selects one of a first reference signal and a second reference signal as an input signal having an input phase. The clock generator receives the input signal and generates a periodic signal, and the periodic signal has an output phase that matches the input phase of the input signal. While the first reference signal is selected as the input signal, the controller identifies a temporal range including a peak instant at which the second reference signal reaches a peak frequency, select a switching instant within the temporal range based on a known temporal position of the peak instant with respect to the temporal range, and control the selector to select the second reference signal as the input signal at the switching instant.

Methods and systems for controlling frequency and phase variations for PLL reference clocks

This application is directed to frequency controlling in an electronic device (e.g., a retimer of a data link). The electronic device includes a selector, a clock generated, and a controller. The selector selects one of a first reference signal and a second reference signal as an input signal having an input phase. The clock generator receives the input signal and generates a periodic signal with reference to the input signal, and the periodic signal has an output phase that matches the input phase of the input signal. While the first reference signal is selected as the input signal, the controller determines whether the second reference signal is in a temporal range in which the second reference signal reaches a peak frequency and controls the selector to select the second reference signal as the input signal in accordance with a determination that the second reference signal is in the temporal range.

Methods and systems for controlling frequency variation for a PLL reference clock

A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, &#x3b8;. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various &#x3b8; values.

On die jitter tolerance test

A system and a method for communicating configuration data between a source device and a sink are described. An active buffer receives data from an auxiliary communication channel which communicates data between the source device and the sink device. The active buffer modifies data received from the auxiliary communication channel. For example, the active buffer amplifies the received data or electrically reshapes the received data. The modified data is then transmitted from the active buffer to a destination device. In one embodiment, the auxiliary communication channel is bi-directional and upon receiving data from a first device, the active buffer is modified to permit uni-directional transmission of data from the first device to a second device.

Active auxiliary channel buffering

A system and method are disclosed for generating a high accuracy and low power on die reference clock. An LC clock is generated on die and a frequency divider lowers the LC clock frequency to a target reference frequency. An RCO clock is generated on die with an unknown initial frequency. The RCO clock and target reference clock are compared to determine in which direction the frequency of the RCO clock should be adjusted to move closer to the target reference frequency. A signal is sent causing a current source or capacitor in the RCO circuit to be modified. Therefore, the RCO clock frequency is adjusted. The RCO circuit is repeatedly adjusted until the RCO clock frequency is sufficiently accurate. The LC clock is disabled to conserve the power that would have been consumed in generating the LC clock.

On die low power high accuracy reference clock generation

A system and a method for exchanging communication data between devices using a bi-directional communication channel are disclosed. A combiner is coupled to a source device via first bi-directional configuration channel and to a sink device via a second bi-directional configuration channel. Upon receiving data from the first bi-directional configuration channel and not receiving data from the second bi-directional configuration channel, the combiner transmits the received data to the sink device using the second bi-directional configuration channel and prevents data transmission from the sink device to the source device using the second bi-directional configuration channel. Similarly, upon receiving data from the second bi-directional configuration channel and not receiving from the first bi-directional configuration channel, the combiner prevents data transmission from the source device to the sink device and transmits the received data to the source device using the first bi-directional configuration channel.

DisplayPort auxiliary channel active buffer with auxiliary channel/display data channel combiner for fast auxiliary channel

Systems and methods provide current mode logic buffers and interface circuits. As an example, in accordance with an embodiment of the present invention, a CML buffer is disclosed that receives and/or provides multiple signal pairs having different common mode voltages to operate over a wider common mode voltage range.

Current mode logic buffer

High speed CML logic gate systems for providing selected Boolean logic functions. Two halves of a substantially symmetric first system, having a relatively small number ( ) of CMOS transistors, are used to generate any of the logic functions AND, NAND, OR and NOR. Two halves of a substantially symmetric second system having another small number ( ) of transistors are used to generate any of the logic functions XOR, XNOR and NOT. In either system, the sum of currents passing through certain voltage-controlling gates is substantially constant.

Symmetrical CML logic gate system

A signal multiplexer system and a signal latch system for low voltage (V &ap;1.2 volts) and high speed transitions between states. A dc signal isolation circuit, inserted between a clock signal circuit and a signal input/output circuit, allows use of a two-transistor-layer vertical structure that provides adequate headroom voltage (about 0.3-0.4 volts, or larger) for high speed transistor response.

Low voltage, high speed CMOS CML latch and MUX devices

A data sampling system, including a data tracking circuit and a data latching circuit, that reduces the likelihood of metastability that arises through competition of the two circuits, where data sampling occurs in a transition time interval. A combined latching and weakened tracking circuit is provided in which the tracking operation cannot change an output signal from the latching operation after the latch resolves a valid logical state.

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San Jose, CA, United States of America

Kochung Lee