Taiwan Semiconductor Manufacturing Comp. Ltd.

Ko-Yi Lee

Yu-Ting Lin

Liang-Chen Lin

Hsi-Yu Kuo

Ta-Chih Peng

Jian-Hsing Lee

Yu-Lin Chu

Pao-Kang Niu

A package structure includes at least one semiconductor chip, an insulating encapsulation, and a redistribution circuit structure. The semiconductor chip has an active surface and connecting pads distributed thereon. The insulating encapsulation encapsulates the semiconductor chip. The redistribution circuit structure is disposed on and has at least one metallization layer with metal segments, wherein the redistribution circuit structure is electrically connected to the semiconductor chip through the at least one metallization layer and the connecting pads electrically connected thereto. A projection location of a first gap between any two most adjacent connecting pads of the connecting pads is partially overlapped with a projection location of a second gap between any two most adjacent metal segments of the metal segments of the at least one metallization layer in a vertical projection on the active surface of the at least one semiconductor chip.

Package structures

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate, the first region comprising a first n type material; a second region over the substrate and laterally adjacent to the first region, the second region comprising a first p type material; a third region disposed within the second region and laterally separated from the first region, the third region comprising a second n type material; a fourth region disposed atop the third region, the fourth region comprising a second p type material; a fifth region disposed within the first region and laterally separated from the second region, the fifth region comprising a third p type material; and a sixth region disposed atop the fifth region, the sixth region comprising a third n type material.

Semiconductor device and method of forming the same

A test structure to detect vertical leakage in a multi-layer flip chip pad stack or similar semiconductor device. The test structure is integrated into the semiconductor device when it is fabricated. A metal layer includes at least two portions that are electrically isolated from each other; one portion being disposed under a test pad, and another portion being disposed under a pad associated with a pad structure being tested. The metal layer in most cases is separated from a top metal layer directly underlying the pads by an inter-metal dielectric (IMD) layer. A metal layer portion underlying the pad to be tested forms a recess in which a conductive member is disposed without making electrical contact. The conductive line is electrically coupled to a test portion of the same or, alternately, of a different metal layer. The test structure may be implemented on multiple layers, with recesses portions underlying the same or different pads.

Test structure

A bonding pad structure and fabrication method thereof. A bonding pad is substantially surrounded and insulated by a dielectric layer, wherein the bonding pad is formed of at least one first conductive layer having a wiring layer with a stripe layout and a first edge portion, a second conductive layer having a wire bonding portion and a second edge portion and a plurality of plugs electrically connecting the wiring layer and the wire bonding portion. A conductive structure of an array of metal plugs or a metal damascene structure is formed to connect the first edge portion and the second edge portion, thereby preventing burn out of the first edge portion during an ESD event.

Growing community of inventors

Hsinchu, Taiwan

Ko-Yi Lee