United Microelectronics Corp.

Ko-Wei Lin

Chun-Ling Lin

Kuo-Chih Lai

Wei Chen

Chun-Yao Yang

Yi-Syun Chou

Huei-Ru Tsai

Hung-Miao Lin

Ying-Lien Chen

Chia-Fu Cheng

Sheng-Yi Su

Chin-Fu Lin

Chia-Chang Hsu

Pei-Hsun Kao

Bin-Siang Tsai

Chun-Yuan Wu

Yen-Chen Chen

Hsin-Fu Huang

Chun-Chieh Chiu

Ai-Sen Liu

Wei-Chuan Tsai

Shih-Min Chou

Yang-Ju Lu

Shu Min Huang

Jen-Po Huang

Tzu-Hao Liu

Seng Wah Liau

Xu Yang Shen

A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.

High electron mobility transistor and method for forming the same

A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

MRAM structure and method of fabricating the same

An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.

Integrated circuit device and method of fabricating integrated circuit

An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

Interconnect structure

Interconnect structure and fabrication method thereof

A method is provided for forming copper material over a substrate. The method includes forming a barrier layer over a substrate. Then, a depositing-soaking-treatment (DST) process is performed over the barrier layer. A copper layer is formed on the cobalt layer. The DST process includes depositing a cobalt layer on the barrier layer. Then, the cobalt layer is soaked with Hgas at a first pressure. The cobalt layer is treated with a Hplasma at a second pressure. The second pressure is lower than the first pressure.

Method for forming copper material over substrate

A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.

Method for fabricating a MIM capacitor

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Taichung, Taiwan

Ko-Wei Lin