International Business Machines Corporation

Massachusetts Institute of Technology

Ko-Tao Lee

Devendra K Sadana

Cheng-Wei Cheng

Kuen-Ting Shiu

Shu-Jen Han

Chia-Yu Chen

Li-Wen Hung

Jui-Hsin Lai

Ghavam G Shahidi

Todd Edward Takken

Frank Robert Libsch

Stephen Mark Rossnagel

Masaharu Kobayashi

Xin Zhang

Ning Li

Keith E Fogel

Tak H Ning

Paul William Coteus

Jeehwan Kim

Hariklia Deligianni

Jeng-Bang Yau

Andrew Ferencz

Joel P Desouza

Takashi Ando

Roy Rongqing Yu

Renee Tong Mo

Seyoung Kim

William Joseph Gallagher

Matthew Warren Copel

Brent A Wacaser

Alessandro Cesare Callegari

John Rozen

Tomas Apostol Palacios

HsinYu Tsai

Pierce I-Jen Chuang

Daniel Piedra

Marinus Johannes Petrus Hopstaken

Shawn Xiaofeng Du

A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.

Direct growth of lateral III-V bipolar transistor on silicon substrate

A Static Random Access Memory (SRAM) device in a binary neural network is provided. The SRAM device includes an SRAM inference engine having an SRAM computation architecture with a forward path that include multiple SRAM cells forming a chain of SRAM cells such that an output of a given one of the multiple SRAM cells is an input to a following one of the multiple SRAM cells. The SRAM computation architecture is configured to compute a prediction from an input. The SRAM computation architecture is configured to store ternary data and perform local computations on the ternary data.

Inference focus for offline training of SRAM inference engine in binary neural network

A Static Random Access Memory (SRAM) device in a binary neural network is provided. The SRAM device includes an SRAM inference engine having an SRAM computation architecture with a forward path that include multiple SRAM cells. The multiple SRAM cells are configured to form a chain of SRAM cells such that an output of a given one of the multiple SRAM cells is an input to a following one of the multiple SRAM cells. The SRAM computation architecture is configured to compute a prediction from an input.

Technical solutions are described for implementing an optogenetics treatment using a probe and probe controller are described. A probe controller controls a probe to perform the method that includes emitting, by a light source of the probe, the probe is embeddable in a tissue, a light wave to interact with a corresponding chemical in one or more cells in the tissue. The method further includes capturing, by a sensor of the probe, a spectroscopy of the light wave interacting with the corresponding chemical. The method further includes sending, by the probe, the spectroscopy to an analysis system. The method further includes receiving, by the probe, from the analysis system, adjusted parameters for the light source, and adjusting, by a controller of the probe, settings of the light source according to the received adjusted parameters to emit a different light wave to interact with the corresponding chemical.

Cognitive optogenetics probe and analysis

The semiconductor structure includes a semiconductor-on-insulator (SOI) substrate. A group III nitride transistor is formed in a trench in the SOI substrate. The activation of the group III nitride transistor is controlled by a silicon-based transistor. The silicon-based transistor that includes a portion of a silicon layer of the SOI substrate. A group III nitride transistor device is adjacent to the silicon-based transistor.

Integrated power amplifier

A hard mask and a method of creating thereof are provided. A first layer is deposited that is configured to provide at least one of a chemical and a mechanical adhesion to a layer immediately below it. A second layer is deposited having an etch selectivity that is faster than the first layer. A third layer is deposited having an etch selectivity that is slower than the first and second layers. The third layer has a composite strength that is higher than the first and second layers. A photoresist layer is deposited on top of the third layer and chemically removed above an inner opening. The third layer and part of the second layer are anisotropically etched through the inner opening. The second layer and the first layer are isotropically etched to create overhang regions of the third layer.

Self-aligned, over etched hard mask fabrication method and structure

A solid state electrochemical battery fabrication device and a method of creating the solid state electrochemical battery are provided. There is a first chamber comprising a first magnetron and a second chamber comprising a second magnetron, coupled to the first chamber. There is a third chamber comprising a vapor source for a polymer deposition, coupled to the second chamber. A Knudsen cell is coupled to the third chamber and configured to deposit lithium on a battery being fabricated. A linear hollow shaft connects the first, second, and third chambers, and provides a hermetic seal. A first telescopic arm having a housing is coupled to a first end of the hollow shaft and configured to extend out of its housing from the first chamber to the second chamber.

Tool and method of fabricating a self-aligned solid state thin film battery

One silicon MOSFET transistor, which is used as the Vcontrol, and a GaN power HEMT are integrated on a single die to enable a fully integrated depletion-mode power device. GaN area is created on a silicon substrate and GaN FETs are built in the GaN area. Outside of the GaN area, silicon transistors such as switch MOSFETs are built. Front end of line or back end of line metal connections are then made to create interconnections among the GaN FET and the silicon transistor. The short physical proximity of the silicon transistor and GaN HEMT significantly reduces the parasitic resistance and inductance between them. Thus, high speed signals are able to travel from the silicon transistor to the GaN HEMT with a higher frequency and lower distortion, without creating overshoot voltage when there is large parasitic inductance. Therefore, the cascode device can operate at a higher switching frequency.

Ultra low parasitic inductance integrated cascode GaN devices

A method for fabricating a semiconductor device includes, for a substrate having a first region protected by a cap layer, forming a first device on a second region of the substrate. The substrate includes an insulator layer disposed between a first semiconductor layer and a second semiconductor layer each including a first semiconductor material. The method further includes forming a second device on the first region, including forming one or more transistors each having a channel formed from a second semiconductor material different from the first semiconductor material.

High switching frequency, low loss and small form factor fully integrated power stage

Methods of fabricating a probe are described. In an example, a structure may be formed on a surface of a substrate. The structure may include the probe, a hinge, and an anchor arranged linearly, where an angle is formed between the probe and the hinge. The hinge may be positioned between the probe and the anchor, and the structure may be parallel to the substrate. An amount of solder may be deposited on an area of the structure that spans from a portion of the probe to a portion of the anchor, and across the hinge. The deposited solder may be reshaped by an execution of a solder reflow process. The reshape of the deposited solder may cause the probe to rotate about the hinge in order to reduce the angle between the probe and the hinge.

Planar fabrication of micro-needles

A method of fabricating an n-type field effect transistor device (nFET) in a region of a wafer element is provided. The method includes forming a mandrel in the region and growing III-V semiconductor materials on the mandrel. The method also includes pulling the mandrel from a gate space in which a capped gate structure is formable and from source and drain (S/D) contact spaces and growing III-V semiconductor materials in the S/D contact spaces.

III-V CMOS co-integration

An approach to forming a full color micro-display that includes using a plurality of micro-light emitting diodes formed in a silicon on insulator substrate, where the plurality of micro-light emitting diodes include a plurality of red micro-light emitting diodes, a plurality of green micro-light emitting diodes, and a plurality of blue micro-light emitting diodes. Additionally, the approach includes forming a plurality of transistor devices in the silicon on insulator substrate, wherein each transistor device of the plurality of transistor devices acts as a switch connecting to a micro-light emitting diode of the plurality of micro-light emitting diodes.

Monolithically integrated GaN light-emitting diode with silicon transistor for displays

A method of forming a multi-state nanosheet transistor device is provided. The method includes forming an alternating sequence of sacrificial layer segments and differentially doped nanosheet layer segments on a substrate, wherein each of the differentially doped nanosheet layer segments has a different dopant concentration from the other differentially doped nanosheet layer segments. The method further includes forming a source/drain on each of opposite ends of the sacrificial layer segments and differentially doped nanosheet layer segments, and removing the sacrificial layer segments. The method further includes depositing a gate dielectric layer on the differentially doped nanosheet layer segments, and forming a gate electrode on the gate dielectric layer to form a common gate-all-around structure, where each of the differentially doped nanosheet layer segments conducts current at a different threshold voltage.

Multi-state transistor devices with multiple threshold voltage channels

Probes include a probe body configured to penetrate biological tissue. High-efficiency light sources are positioned within the probe body. Each high-efficiency light source has a sufficiently intense light output to trigger a light-sensitive reaction in neighboring tissues and has a sufficiently low power output such that a combined heat output of multiple light sources does cause a disruptive temperature increase in the neighboring tissues.

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Yorktown Heights, NY, United States of America

Ko-Tao Lee