Nec Corporation

Nec Electronics Corporation

Ko Noguchi

Shinya Ito

Yoshihisa Matsubara

Takashi Ishigami

Noriaki Oda

Akira Matsumoto

Toru Tatsumi

Kazuhiko Endo

Tadahiko Horiuchi

Masahiko Nakamae

Yoshishige Matsumoto

A semiconductor device having a metal oxide semiconductor (MOS) transistor with a gate dielectric film, a gate electrode formed on the gate dielectric film, and source/drain regions formed in a semiconductor substrate. A protective element with a protected electrode overlays of the semiconductor substrate with an intervention of a dielectric film. At least one diffused region is adjacent to the protective electrode in the semiconductor substrate. The protect dielectric is connected to the electrode of the MOS transistor.

Semiconductor device with protective element

A circuit design method for designing conductive members with a multilayered structure to have antenna sizes of proper values is disclosed. Individual damage is calculated for each of a plurality of antenna units of the conductive members with a multilayered structure, and an integrated circuit device is designed such that a total amount of the separately calculated individual damage is less than a predetermined permissible amount. It is possible to accurately calculate a total amount of damage to a gate insulating film even when the plurality of antenna units of the conductive members with a multilayered structure have different degrees of damage and antenna ratios from one another, and an integrated circuit device of optimal structure can be designed with high efficiency.

Circuit design method for designing conductive members with a multilayered structure to have antenna sized of proper values

A system for estimating a plasma damage for subsequent layout design of a semiconductor device includes an antenna ratio extraction unit for extracting an antenna ratio from each of existing provisional layout patterns to be exposed to plasma in each of plasma processes. An index calculation unit is connected to the antenna ratio extraction unit for receiving the antenna ratio extracted by the antenna ratio extraction unit and calculating an individual damage index representing a degree of a plasma damage in accordance with the antenna ratio. An index addition unit is connected to the index calculation unit for receiving the individual damage indexes from the index calculation unit and adding the individual damage indexes to estimate a plasma damage.

Method and system for estimating plasma damage to semiconductor device for layout design

Antenna size of conductive members is calculated with respect to an area of a gate oxide film of a transistor using an expression which approximates an actual relationship of changes therein, not using a simple proportional relationship. As a result, in design of a structure having conductive members connected to a gate oxide film of a transistor, it is possible to properly calculate an antenna size such as wire length of the conductive members with respect to an area of the gate oxide film.

Circuit design method calculating antenna size of conductive member connected to gate oxide film of transistor with approximate expression

A structure and manufacturing process of a low dielectric constant interlayer insulating film used between wiring layers and semiconductor devices using such film are disclosed. The insulating film which can withstand in an actual process comprises an amorphous carbon fluoride film. A diamond like carbon film and a silicon excess layer are disposed on both sides of the amorphous carbon fluoride film to be inserted between the wiring layers, whereby adhesion to wiring and another insulating film contacting it is significantly enhanced. In addition, a silicon based insulating film is disposed and flattened on a multilayer film containing an amorphous carbon fluoride film buried with a wiring layer, and is used as a hard mask for anisotropically etching the diamond like carbon film and the amorphous carbon fluoride film with oxygen plasma to form a via hole.

Insulating film comprising amorphous carbon fluoride, a semiconductor device comprising such an insulating film, and a method for manufacturing the semiconductor device

The invention provides a semiconductor device that has sufficient device protection capability and besides allows integration of transistors with high density. The semiconductor device includes an NMOS transistor formed in a p-well on a p-type substrate, an n-well formed adjacent the p-well, and first and second protection elements connected to a gate electrode of the NMOS transistor. The first protection element is a pn diode formed from the p-well and an n diffusion region provided in the p-well and lets negative charges escape to the p-type substrate. The second protection element is a pn diode formed from the n-well and a p diffusion region provided in the n-well, and lets positive charges escape to the p-type substrate as pn junction leakage current between the n-well and the p-type substrate. In order to increase the area of the n-well that forms the protection element, the semiconductor device further includes a second p-well provided adjacent the first n-well, an n-type buried well formed below the second p-well, and a second n-well connected to the first n-well through the n-type buried well.

Semiconductor protection device

In a semiconductor device comprising a first level insulator film formed on a silicon substrate, a first level wiring conductor formed on the first level insulator film, and a second level insulator film formed to cover the first level wiring conductor and the first level insulator film, openings are formed in the second level insulator film, and second level wiring conductors are formed to fill up the openings. The openings including a through-hole type opening and at least two groove type openings having different depths, and the through-hole type opening extends through one of the at least two groove type openings to reach the first level wiring conductor. The grooved wiring conductors having different film thicknesses are provided in the same wiring conductor level.

Grooved wiring structure in semiconductor device and method for forming the same

A method of manufacturing a semiconductor device includes (a) providing a semiconductor substrate of a first conductive type, (b) forming a field insulating film on the semiconductor substrate, and (c) providing a first region and a second region in which the field insulating film is not formed on the semiconductor substrate. Also, the method includes (d) forming a gate insulating film on both the first region and the second region at a same time, (e) removing the gate insulating film formed on the second region to expose a surface portion of the semiconductor substrate, and (f) forming a diffusion layer of the first conductive type in the second region from which the gate insulating film is removed. Further, the method includes (g) forming a gate electrode after the (f) step such that the gate electrode is in contact with at least a portion of respective the first region and the second region and (h) changing the diffusion layer into a diffusion layer of a second conductive type different from the first conductive type, after the (g) step.

Method of manufacturing semiconductor device in which damage to gate insulating film can be reduced

A semiconductor device includes a protective element which is formed on a semiconductor substrate and conducts current to the semiconductor substrate at a voltage lower than the breakdown voltage of an insulating layer formed between a gate electrode and the semiconductor substrate. The protective element is connected to a gate electrode of a MOS transistor formed on the semiconductor substrate.

Semiconductor device having protective element to conduct current to substrate

Grooved wiring structure in semiconductor device and method for forming

Insulating film comprising amorphous carbon fluoride, a semiconductor

In a semiconductor device, a metal oxide semiconductor (MOS) transistor is formed on a semiconductor substrate to have a gate electrode which is formed on a gate oxide film. The first insulating layer is formed to cover the semiconductor substrate and the MOS transistor. The second insulating layer is formed to cover the first insulating layer. The first wiring structure is formed on the first insulating layer. A part of the first wiring structure passes through the second insulating layer. The second wiring structure is not connected to the first wiring structure, and passes through the first and second insulating layers to be connected to the gate electrode. The second wiring structure has an antenna ratio of equal to or less than 1000. The third wiring structure is connected to the first and second wiring structures and formed on the second insulating layer to have the antenna ratio of equal to or less than 1000. Here, the antenna ratio is a ratio of surface area of a wiring structure to surface area of a gate oxide film.

Semiconductor device and method of manufacturing the same in which

In a semiconductor device including a first insulating layer formed on a semiconductor substrate, a plurality of lower wiring layers made of one of aluminum and aluminum alloy and formed on the first insulating layer, a second insulating layer made of one of silicon oxide and PSG and formed on the first insulating layer, and a plurality of upper wiring layers made of one of aluminum and aluminum alloy, contact holes having a size larger than a width of the lower wiring layers are formed within the second insulating layer, and contact plugs are filled in the contact holes. Also, a conductive layer including one of Ti and W is provided between the lower wiring layers and the contact plugs.

Semiconductor device having capped contact plug capable of suppressing

A gate electrode of a field effect transistor is charged during a plasma process, and a gate oxide layer is liable to be damaged; a protective junction diode is connected to the gate electrode of the field effect transistor, and is radiated with light during the plasma process so as to increase leakage current passing through the p-n junction; the leakage current is increased before the breakdown of the protective junction diode so as to prevent the gate oxide layer from the electric charge, and the breakdown voltage is higher than a test voltage applied to the gate electrode during a diagnosis on the gate oxide layer so that the manufacturer exactly diagnoses the semiconductor device.

Semiconductor device having field effect transistor connected at gate

A high voltage semiconductor device includes a low voltage CMOSFET and a p-channel high voltage MOSFET having a drain formed in a p-well and a source in an n-well. The p-well has a bottom flush with the bottom of the n-well, and a heavily doped n-well is further provided at the bottom surface of the p-well at least a part of the bottom surface of the n-well. The high voltage MOSFET has a large rated voltage and is suited for fabrication in a finer structure.

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Tokyo, Japan

Ko Noguchi