Freescale Semiconductor,inc.

Motorola Corporation

Other

Nxp Usa, Inc.

Ko-Min Chang

Cheong Min Hong

Clinton C Kuo

Feng Zhou

Craig T Swift

Bruce L Morton

Kuo-Tung Chang

Erwin J Prinz

Gowrishankar L Chindalore

Brian A Winstead

Frank Kelsey Baker, Jr

Robert F Steimle

Craig A Cavins

Danny P Shum

Marius K Orlowski

Anirban Roy

Michael Alan Sadd

Sung-Taeg Kang

Alexander Hoefler

Jane A Yater

Keith E Witek

Ming-Bing Chang

Kent J Cooper

Henry Y Choe

Ramachandran Muralidhar

Rajesh A Rao

Konstantin V Loiko

Hsing-Huang Tseng

Asanga H Perera

Matthew Thomas Herrick

Shih-Wei Sun

Philip S Smith

Douglas R Roberts

Chi Nan Brian Li

Peter J Kuhn

George L Espinor

Wei-Ming Chen

Jinmiao James Shen

William J Taylor

Taras A Kirichenko

Mark S Weidner

Mohammed Suhail

Shiang-Chyong Luo

Keith Forbes

A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate.

Structures for split gate memory cell scaling with merged control gates

A semiconductor device includes a semiconductor substrate, a charge storage stack over a portion of the substrate. The charge storage stack includes a first dielectric layer, a layer of nanocrystals in contact with the first dielectric layer, a second dielectric layer over and in contact with the layer of nanocrystals, a nitride layer over and in contact with the second dielectric layer, and a third dielectric layer over the nitride layer.

Split gate memory cell with a layer of nanocrystals with improved erase performance

Methods and structures for split gate memory cell scaling with merged control gates

Forming a memory structure includes forming a charge storage layer over a substrate; forming a first control gate layer; patterning the first control gate layer to form an opening in the first control gate layer and the charge storage layer, wherein the opening extends into the substrate; filling the opening with an insulating material; forming a second control gate layer over the patterned first control gate layer and the insulating material; patterning the second control gate layer to form a first control gate electrode and a second control gate electrode, wherein the first control gate electrode comprises a first portion of each of the first and second control gate layers and the second control gate electrode comprises a second portion of each of the first and second control gate layers, and the insulating material is between the control gate electrodes; and forming select gate electrodes adjacent the control gate electrodes.

Methods and structures for charge storage isolation in split-gate memory arrays

A resistive random access memory (ReRAM) cell, comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and an interface region comprising a plurality of interspersed field focusing features that are not photo-lithographically defined. The interface region is located between the first conductive electrode and the dielectric storage material layer or between the dielectric storage material layer and the second conductive electrode.

Field focusing features in a ReRAM cell

A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters () including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.

A resistive random access memory (ReRAM) includes a first metal layer having a first metal and a metal-oxide layer on the first metal layer. The metal-oxide layer includes the first metal. The ReRAM further includes a second metal layer over the metal-oxide layer and a first continuous conductive barrier layer in physical contact with sidewalls of the first metal layer and of the metal-oxide layer.

ReRAM device structure

A resistive random access memory cell uses a substrate and includes a gate stack over the substrate. The gate stack includes a first copper layer over the substrate, a copper oxide layer over the first copper layer, and a second copper layer over the copper oxide layer.

Resistive random access memory (RAM) cell and method for forming

A resistive random access memory (ReRAM) includes a first metal layer having a first metal and a metal-oxide layer on the first metal layer. The metal-oxide layer inlcudes the first metal. The ReRAM further includes a second metal layer over the metal-oxide layer and a first continuous conductive barrier layer in physical contact with sidewalls of the first metal layer and of the metal-oxide layer.

A method for forming a split gate device includes forming a first sidewall of a first conductive gate layer, wherein the semiconductor layer includes a tunnel region laterally adjacent the first sidewall, forming a dielectric layer along the first sidewall to provide for increased thickness of a gap spacer, forming a charge storage layer over a portion of a top surface of the first conductive layer and over the tunnel region, and forming a second conductive gate layer over the charge storage layer.

Split gate memory device with gap spacer

A method includes forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer; forming an opening; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gate material over the charge storage layer; removing a portion of the second layer and a portion of the charge storage layer which overlie the hard mask layer, wherein a second portion of the second layer remains within the opening; forming a patterned masking layer over the hard mask layer and over the second portion, wherein the patterned masking layer defines both a first and second bitcell; and forming the first and second bitcell using the patterned masking layer, wherein each of the first and second bitcell comprises a select gate made from the first layer and a control gate made from the second layer.

Method of making a split gate memory cell

Testing a non volatile memory by exposing the non volatile memory to particle radiation (e.g. xenon ions) to emulate memory cell damage due to data state changing events of a non volatile memory cell. After the exposing, the memory cells are subjected to tests and the results of the tests are used to develop reliability indications of the non volatile memory. Integrated circuits with non volatile memories of the same design are provided. Reliability representations of the integrated circuits can be made with respect to a number of data state charging events based on the exposure and subsequent tests.

Method for simulating long-term performance of a non-volatile memory by exposing the non-volatile memory to heavy-ion radiation

A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device () by forming a select gate structure () on a first dielectric layer () over a substrate (); forming a control gate structure () on a second dielectric layer () having embedded nanocrystals () so that the control gate () is adjacent to the select gate structure () but separated therefrom by a gap (); forming a floating doped region () in the substrate () below the gap () formed between the select gate structure and control gate structure; and forming source/drain regions () in the substrate to define a channel region that includes the floating doped region ().

Split-gate thin film storage NVM cell with reduced load-up/trap-up effects

A memory device is formed on a semiconductor substrate. A select gate electrode and a control gate electrode are formed adjacent to one another. One of either the select gate electrode or the control gate electrodes is recessed with respect to the other. The recess allows for a manufacturable process with which to form silicided surfaces on both the select gate electrode and the control gate electrode.

Silicided nonvolatile memory and method of making same

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Austin, TX, United States of America

Ko-Min Chang