Powerchip Semiconductor Corporation

Worldwide Semiconductor Manufacturing Corporation

Ko-Hsing Chang

Chiu-Tsung Huang

Cheng-Yuan Hsu

Hann-Jye Hsu

Su-Yuan Chang

Tsung-Cheng Huang

Ling-Sung Wang

Yan-Hung Huang

Yeur-Luen Tu

Chih-Ming Chen

Chen-Chiu Hsue

Chine-Gie Lou

Chih-Wei Hung

Tung-Po Chen

Tung-Ming Lai

Horng-Ming Lee

Kuo-Hao Juo

Chen-Hsi Lin

Wu-Tsung Chung

A method of manufacturing of a photodiode is provided. The photodiode is formed on a substrate of a first conductive type. First, an isolation structure is formed in the substrate to define a photosensitive area in the substrate. Thereafter, trenches are formed in the substrate. Next, a doped layer of a second conductive type is formed on the substrate. The doped layer covers at least the inner wall of the trenches and a top portion of the substrate. The method of fabricating the photodiode can reduce overall processing time and cost and improve production efficiency.

Method of manufacturing photodiode

A non-volatile memory is provided. An assist gate structure is formed on a substrate such that the width at the bottom of the assist gate structure is greater than the width at the top of the assist gate structure. A floating gate is formed on one side of the assist gate structure and disposed between a word line and the substrate. The width at the bottom of the floating gate is smaller than the width at the top of the floating gate. The word line, the floating gate and the assist gate structure together form a memory unit. A tunneling dielectric layer is formed between the floating gate and the substrate. An inter-gate dielectric layer is formed between the word line, the floating gate and the assist gate structure. Source/drain regions are formed in the substrate on the respective sides of the memory unit.

Non-volatile memory including assist gate

A one time programmable memory including a substrate, a plurality of isolation structures, a first transistor, and a second transistor is provided. The isolation structures are disposed in the substrate for defining an active area. A recess is formed on each of the isolation structures so that the top surface of the isolation structure is lower than that of the substrate. The first transistor is disposed on the active area of the substrate and is extended to the sidewall of the recess. The gate of the first transistor is a select gate. The second transistor is disposed on the active area of the substrate and is connected to the first transistor in series. The gate of the second transistor is a floating gate which is disposed across the substrate between the isolation structures in blocks and is extended to the sidewall of the recess.

One time programmable memory and the manufacturing method thereof

A non-volatile memory is provided, including a substrate, a control gate, a floating gate, and a select gate. A source region and a drain region are disposed in the substrate. The control gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed between the control gate and the substrate. The cross-section of the floating gate presents, for example, an L-shape and the floating gate includes a central region which is perpendicular to the substrate and a lateral region which is parallel to the substrate. The central region is adjacent to the source region. The select gate is disposed on the sidewall of the control gate and the lateral region of the floating gate, and is adjacent to the drain region. Besides, the present invention further includes a method of manufacturing the above non-volatile memory.

Non-volatile memory

A method for fabricating a non-volatile memory is described. A substrate having isolation structures is provided. These isolation structures protrude from the substrate, and a first mask layer is formed on the substrate between the isolation structures. A second mask layer is formed on the substrate. The second and the first mask layers are patterned to form openings exposing part of the surface of the substrate and the isolation structures. A tunneling dielectric layer and a first conductive layer are formed on the substrate. The first conductive layer is filled in the opening, and is divided into blocks by the isolation structures, the second mask layer, and the first mask layer. An inter-gate dielectric layer is formed on the substrate. A second conductive layer is formed on the substrate to fill up the openings. Doped regions are formed in the substrate on both sides of the second conductive layer.

Fabricating method of non-volatile memory

A non-volatile memory is described, including a substrate, a floating gate, a control gate, a source region, and a drain region. A trench is disposed in the substrate, and a step-like recess is located in the substrate beside the trench. The floating gate is disposed on the sidewall of the trench. The control gate is disposed on the substrate between the trench and the step-like recess which extends in the step-like recess. The source region is disposed in the substrate at the bottom of the trench. The drain region is disposed in the substrate at the bottom of the step-like recess.

Non-volatile memory and manufacturing method thereof

A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate structures each including a tunneling dielectric layer, a floating gate and a cap layer are formed on the active layers. The inter-gate dielectric layers are formed on the sidewalls of the stacked gate structures. The select gates are formed on one side of the stacked gate structure and across the active layer. The select gate dielectric layers are formed between the select gates and the active layers. The source regions are formed in the active layers on the other side of the stacked gate structures. The drain regions are formed in the active layers on one side of the select gates.

Split gate flash memory

A flash memory cell and a method for fabricating the same are described. The flash memory cell comprises a substrate, a select gate, a floating gate, a gate dielectric layer, a high-voltage doped region and a source region. The substrate has a first opening thereon and a second opening in the first opening. The select gate is on the sidewall of the first opening, and the floating gate is on the sidewall of the second opening. The gate dielectric layer is between the select/floating gate and the substrate. The high-voltage doped region is in the substrate under the second opening, and the source region is in the substrate beside the first opening. In the method of fabricating the flash memory cell, the select gate and the floating gate are simultaneously formed on the side walls of the first opening and the second opening, respectively.

Flash memory cell and fabricating method thereof

A multi-level memory cell including a substrate, a tunneling dielectric layer, a charge-trapping layer, a top dielectric layer, a gate and a pair of source/drain regions is provided. The tunneling dielectric layer, the charge-trapping layer and the top dielectric layer are sequentially formed between the substrate and the gate. The top dielectric layer has at least two portions, and the top dielectric layer in each portion has a different thickness. The source/drain regions are disposed in the substrate on each side of the gate. Since the thickness of the top dielectric layer in each portion is different, the electric field strength between the gate and the substrate when a voltage is applied to the memory cell are different in each portion. With the number of charges trapped within the charge-trapping layer different in each portion, a multiple of data bits can be stored within each memory cell.

Multi-level memory cell

A multi-level memory cell includes a substrate, an insulation layer, a silicon stripe, a first control gate, a second control gate, source/drain regions, silicon oxide/silicon nitride/silicon oxide composite layers. The insulation layer and the silicon stripe are sequentially disposed on the substrate. The first control gate and the second control gate are respectively disposed on the sidewalls of the silicon stripe, while the source/drain regions are configured in the silicon stripe beside both sides of the first control gate and the second control gate. The composite dielectric layers are disposed between the first control gate and the silicon stripe, and between the second control gate and the silicon stripe. Since a single memory structure can store a multiple bit of information, it is advantageous for minimizing devices.

Multi-level memory cell and fabricating method thereof

A non-volatile memory device and method of manufacturing the same is provided. A substrate is provided and then a trench is formed in the substrate. Thereafter, a bottom oxide layer, a charge-trapping layer and a top oxide layer are sequentially formed over the substrate and the surface of the trench. A conductive layer is formed over the top oxide layer filling the trench. The conductive layer is patterned to form a gate over the trench. The top oxide layer, the charge-trapping layer and the bottom oxide layer outside the gate are removed. A source/drain doping process is carried out. Because the non-volatile memory device is manufactured within the trench, storage efficiency of the device is improved through an increase in the coupling ratio. Furthermore, more charges can be stored by increasing the depth of the trench.

Non-volatile memory device and method of manufacturing the same

A method for manufacturing an OTEPROM is described. A tunneling oxide layer, a first conductive layer, a first patterned mask layer are formed on a substrate. A trench is formed in the substrate. An insulating layer is formed to fill the trench. A portion of the first conductive layer destined to form the floating gate is exposed and then a cap layer is formed thereon. The first patterned mask layer is removed and then a second conductive layer and a second patterned mask layer are formed over the substrate. A word line and a floating gate are formed using the second patterned mask layer and the cap layer as a mask. The second patterned mask layer is removed and then source/drain regions are formed in the substrate on both sides of the word line and the floating gate and between the word line and the floating gate.

Method for manufacturing one-time electrically programmable read only memory

A method of manufacturing a semiconductor device. The method comprises steps of providing a substrate having a first metal layer and a second metal layer formed thereon. A first dielectric layer, an etching stop layer having a first opening located above the first metal layer and a second opening located above the second metal layer and a second dielectric layer are formed sequentially. A portion of the first dielectric layer and a portion of the second dielectric layer are removed to form a first trench exposing the first metal layer. A capacitor dielectric layer is formed over the substrate. A third opening is formed in the capacitor dielectric layer. A portion of the second dielectric layer and a portion of the first dielectric layer exposed by the third opening are removed to form an opening. A metal layer is formed to fill out the first trench and the opening.

Method of manufacturing semiconductor device

A method of manufacturing a non-volatile memory cell includes forming a bottom dielectric layer and a charge trapping layer on a substrate sequentially. The electron trapping layer is patterned to form a trench exposing a portion of the bottom dielectric layer. A top dielectric layer is formed over the substrate and covers the electron trapping layer and the exposed bottom dielectric layer. A conductive layer is then formed on the top dielectric layer. The conductive layer, the top dielectric layer, the electron trapping layer and the bottom dielectric layer are patterned to form a stacked structure, wherein a width of the stacked structure is larger than a width of the trench. A source/drain region is formed in the substrate adjacent to the edges of the stacked structure. Because the electron trapping layer of the memory cell is divided into two isolation structures according to the invention, it is adapted for the integration of devices and for long-time operation.

Method of fabricating non-volatile memory cell adapted for integration of devices and for multiple read/write operations

A non-volatile memory cell is provided. The non-volatile memory at least includes a substrate, a gate, a first source/drain region, a composite dielectric layer and a second source/drain region. A trench is formed in a substrate and a gate is formed inside the trench. The first source/drain region is formed at the bottom of the trench. The composite dielectric layer is formed between the gate and the surface of the trench. The composite dielectric layer includes at least a charge-trapping layer. The second source/drain region is formed in the substrate next to the sides of the gate.

Growing community of inventors

Hsinchu, Taiwan

Ko-Hsing Chang