International Business Machines Corporation

Knut K Najmann

Wilfried Klein

Klaus Heuber

Siegfried K Wiedmann

Friedrich C Wernicke

Rolf Remshardt

Erich Klink

Wayne Frederick Ellis

Marian Briska

Arnold Blum

Werner O Haug

Horst H Berger

Helmut H Heimeier

Utz G Baitinger

Klaus Tertel

A semiconductor packaging subassembly is described in which a plurality of modules or chips, repsonsive to a plurality of common input signals, are provided with input signal redriver circuits. Each redriver circuit is responsive to an input and provides an output signal to each the of chips in the subassembly. The preferred embodiment is directed to a multi-module memory arrangement in which input signals including CAS, RAS, W and address signals are received and redriven.

Input signal redriver for semiconductor modules

An integrated (silicon based) packaging/wiring structure provides for VLSI chips 4 to be placed within openings of somewhat larger size in a semiconductor interconnection wafer (IW, 2) supported by a carrier 1. The interconnection wafer 2 includes multilevel (ML) wiring planes and incorporated circuit components integrated in a less demanding technology as compared to the VLSI chips 4. Silicon contact chips 5 with conductive surface layers 22, 23 placed over the chip/IW plane provide for the required interconnections by means of needle-like structures 24 inserted in corresponding via holes. The needles are better suited to withstand shear strain than are conventional C-4 (Controlled Collapse Chip Connection) joints. Consequently a much higher number of chip pads can be provided. Power supply is effected via rather large-dimensioned conductive planes, e.g. in the form of Cu rails 20, running within the carrier 1 and surfacing stud-like (at 21) in the peripheral region of said openings in the interconnection wafer 2 for further distribution via the contact chip 5. The wiring system can be supplemented, if required, with an additional wiring wafer 6.

Integrated wiring system for VLSI

Disclosed is a phase splitter with integrated latch circuit, where the complementary output signals generated after an input signal applied to a true-complement generator are available directly without any load by the latch circuit, where upon a premature change of the input signal there is no undesired change of the previously set switching state or of the output signals, respectively, and where a simple clocking for functional control can be used. The advantages presented by the disclosed Phase splitter substantially consist in that the speed with which the complementary output signals are supplied is extremely high since the output signals are available directly, i.e. with only one stage delay, the latch circuit being non-conductive in the stationary state, and thus in a latching process does not have to be switched from one stage to the other, but only switched on.

Phase splitter with integrated latch circuit

An integrated semiconductor memory having memory cells which have (or are designed to have) inherent asymmetrical access times for the distinguishable memory states thereof. The memory is operated on the basis of the shorter access time. This is accomplished by utilizing an oppositely asymmetrical sense system, preferably in the form of a pre-set sense latch. For example, in the case of a digital memory with the reading of a '0' state having a shorter access time than the reading of a '1' state, at the beginning of a read operation a sense latch is set to the (slower) '1' state. Thus, only in the case of reading a '0' is the state of the latch changed to the '0' state. Thus, the actual access time is no longer determined by the longer access time, namely, the reading of a '1'. The access time is determined by the shorter access time, namely, the reading of a '0'. The concept may also be used if the sense latch has an asymmetric access time. Then it is advantageous to intentionally choose a corresponding asymetrical memory cell design.

Integrated semiconductor memory and method of operating same

A memory storage system which utilizes semiconductor storage cells comprised of cross-coupled bipolar transistors arranged in a memory system array with an error reference circuit and a standby reference circuit that is controlled by a clock signal. The standby reference circuit and the error reference circuit are both coupled to the bit lines and selectively control a restore circuit that maintains, in the standby state, a selected potential on the bit lines such that short access times are realized and current is prevented from flowing into unselected cells when adjacent defective cells are being read or written.

Memory storage array with restore circuit

The invention relates to a circuit arrangement for operating the read/write cycles of an integrated semiconductor memory storage system whose storage cells consist of flip flops with bipolar switching transistors, Schottky diodes as read/write elements coupling the cell to the bit lines, and high-resistivity resistors, or transistors controlled as current sources, as load elements, in several phases. This is accomplished through coupling the storage cell to both read/write circuits and restore/recovery circuits via the bit lines and by selective pulsing of the cell with the read/write circuits and the restore/recovery circuits. This permits high speed, low operating current, large scale memory systems to be built.

Circuit arrangement for operating a semiconductor memory system

An improved method of operating a monolithic memory together with novel and efficient circuitry for practicing said improved method is disclosed. In a bipolar transistor store, or monolithic memory, in accordance with the invention, a very low current (first level) flows from the load elements to the internal cell nodes in the stand-by mode. During the initial portion of a read cycle, current flows from the bit lines to the cell nodes, in addition to the stand-by current (second level). In the recovery period of the read cycle or write cycle a short pulse is added to the stand-by current (third level), thereby reducing the recovery time. The practice of the invention provides a monolithic memory having minimal power requirements and a substantially reduced cycle time.

Read/write speed up circuit for integrated data memories

This teaches a sense circuit for an integrated memory storage system in which the storage cell output is detected by a differential amplifier, controlling a flip-flop, serving as a latch, having load elements which also function as the load elements of the latch to ensure an optimum power and speed product. The latch can be coupled to an output driver circuit through a current switch which shares common elements with the latch to assure that the latch remains symmetrical even when used with an output driver having asymmetrical control.

Sense circuit for memory storage system

This describes an integrated semiconductor structure having an epitaxial semiconductor layer, divided into regions by isolation zones and containing active and passive semiconductor devices, of a first conductivity type on a substrate of the opposite second conductivity type. A reference potential and first and second supply voltages are applied to the structure. An additional isolated transistor, in accordance with this invention prevents an unlimited current flow, via the chip isolation junction, from one voltage supply to the other when the power-on sequence for both voltages is undefined. The base of this additional transistor is connected to one of the voltages via an integrated resistor while the other voltage is connected to the emitter and the collector is connected to the substrate via the isolation zone. Thus, the isolation junction can never become forward biased. In addition, this arrangement ensures that the substrate potential is independent of the rate of the above-mentioned substrate current, and perfect isolation is guaranteed under all conditions.

Integrated semiconductor structure with means to prevent unlimited

Modern bipolar cross coupled memory cells for high density arrays use diodes as coupling elements from the cell to the bit lines. The write operation of these cells requires a high amount of current if the current gain of the cell transistors is high. The time required to perform a write operation is prolonged significantly due to the inherent capacitors in the cell known as the Miller effect. The described circuit completely eliminates the Miller effect during the write operation and makes the required write current completely independent of the current gain of the cell transistors. In the present invention this is accomplished by dropping the word line of such a cell from a stand-by potential to a select potential, so that the inner cell nodes are equally discharged, without disturbing the state of the cell, after which the word line is pulsed up to an intermediate potential between the select potential and the stand-by potential.

Write speed-up circuit for integrated data memories

A method and circuit arrangement for operating an information store, in particular a monolithic information store, whose storage cells and address circuits comprise bipolar transistors which are not continuously subjected to full power. The monolithic information store is readily fabricated by known planar process technology, has increased density, has reduced read/write times, reduced cycle time, and reduced power dissipation.

Method and circuit arrangement for operating a highly integrated

A semiconductor storage circuit for use in monolithic memories. The circuit is comprised of a storage cell coupled to input-output bit lines through active devices having symmetrical conduction properties. The storage cell can be comprised of a pair of cross coupled bipolar transistors having resistors as collector load devices. Schottky field effect transistors (MESFET's) are active devices having symmetrical conduction properties. The entire circuit of the invention is readily created in integrated form in semiconductor wafers using existing processes.

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Gaertringen, Germany

Knut K Najmann