Deutsche Itt Industries Gmbh

Knut Caesar

Ulrich Schmidt

Arnold Uhlenhoff

Helmut Haeringer

Thomas Himmel

A wavefront array processor where each cell includes a handshake port for asynchronous data transfer with an adjacent cell. The handshake port includes a buffer for receiving data from the adjacent cell and a latch for transferring data to the adjacent cell. Data transfer is accomplished through use of a handshaking protocol which indicates whether or not a receiving buffer is full and if the buffer can receive data. Data can only be transferred if there is room in the buffer to accept the data. The handshaking protocol responds to status signals. A source status signal indicates that a data source has generated a data word. A sink status signal indicates that the buffer can receive data. Each cell further includes a data processing unit, which provides the latch with data and which accesses data from the buffer, and a blocking device, which allows the data processing unit or another handshake port to transfer data to the latch and the buffer to accept data, only when the handshake signals are appropriate. Internal to each cell is a ring bus configuration for distribution of data between the handshake ports and the data processing unit.

Wavefront array processor for blocking the issuance of first handshake

A two-way data transfer device for the data interface between two data-exchanging cells including a data source and a data sink with at least one buffer provided in each cell. When the transmitter buffer is full or the receiver buffer is empty, a backward cell stop signal freezes the state of the data source or the data sink and the cell stop signals are controlled by status signals from the respective buffers.

Two-way data transfer apparatus

A programmable logic array implemented with complementary insulated-gate field effect transistor technology and formed on a substrate employing a standard AND-OR structure and two non-overlapping clock phases uses diffused capacitors in a dummy row to model the worst case evaluation time of minterms in the AND plane, and a NOR gate, responsive to the dummy row, for enabling the OR plane to sum the minterms generated by the AND plane.

Growing community of inventors

Gundelfingen, Germany

Knut Caesar