Infineon Technologies Ag

Klaus Schruefer

Ronald Kakoschke

Christian Pacha

Juergen Holz

Christian Cornelius Russ

Snezana Jenei

Helmut Horst Tews

Thomas Nirschl

Thomas Schulz

Jiang Yan

Henning Haffner

Doris Schmitt-Landsiedel

Richard Lindsay

Frank Huebinger

Hans-Joachim Barth

Sun-Oo Kim

Andreas Rusch

Sunoo Kim

A preferred embodiment includes a method of manufacturing a fuse element that includes forming a polysilicon layer over a semiconductor structure, doping the polysilicon layer with carbon or nitrogen, depositing a metal over the polysilicon layer; and annealing the metal and polysilicon layer to form a silicide in an upper portion of the polysilicon layer.

Silicided semiconductor structure and method of forming the same

A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions.

Field-effect transistor with local source/drain insulation and associated method of production

Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.

Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor

A memory element includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.

Semiconductor device including FinFET device

An electronic circuit arrangement in accordance with some embodiments has a substrate, the substrate including: a plurality of metallization layers located one above the other; a single fuse-link via coupled between a first metallization layer and a second metallization layer of the plurality of metallization layers, wherein the single fuse-link via is in the form of an electrical fuse link preferentially programmable by applying a sufficiently large current to melt or degenerate the fuse link; a plurality of through-contact vias coupled in parallel between a third metallization layer and a fourth metallization layer of the plurality of metallization layers, wherein the through-contact vias form a through-contact between the third and fourth metallization layers; and electrical circuit components, arranged in a circuit layer, which are electrically coupled to one another by means of the single fuse-link via and by means of the plurality of through-contact vias.

Electronic circuit arrangement

An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD) in comparison with other transistors (T) on the same integrated circuit arrangement (). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions (D, S) of the tunnel field effect transistor.

One or more embodiments relate to a memory device, comprising: a memory element; and a FinFET select device including a fin, a gate line supported by the fin, and a contact element coupled between a surface of the fin and the memory element, the contact element being in direct contact with a top surface of the fin.

Apparatus of memory array using FinFETs

Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.

Vertical diode using silicon formed by selective epitaxial growth

Embodiments relate to a bipolar transistor that includes a body region having a fin structure. At least one terminal region may be formed over at least a portion of the body region. The at least one terminal region may be formed as an epitaxially grown region. Embodiments also relate to a vertically integrated electronic device that includes a first terminal region, a second terminal region and a third terminal region. The second terminal region may be arranged over at least a portion of the third terminal region, and at least two of the first, second and third terminal regions may be formed as epitaxially grown regions.

Electronic device and manufacturing method thereof

One or more embodiments relate to a method, comprising forming an implant on a substrate surface; selectively etching the wafer surface to form an elongated fin including portion of the implant; forming collector/emitter regions adjacent opposing ends of the fin; and forming a base region intermediate the collector/emitter regions.

Method of making bipolar FinFET technology

A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized.

Field effect transistor with a heterostructure

A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.

Growing community of inventors

Baldham, Germany

Klaus Schruefer