Infineon Technologies Ag

Intel Mobile Communications Gmbh

Intel Deutschland Gmbh

Klaus Pressel

Gottfried Beer

Thorsten Meyer

Jens G Pohl

Recai Sezi

Markus Brunnbauer

Ralf Plieninger

Stephan Bradl

Jochen Dangelmaier

Horst Theuss

Manfred Mengel

Maciej Wojnowski

Alfred Haimerl

Werner Simbuerger

Christoph Kienmayer

Klaus Mueller

Bernd Waidhas

Walter Hartner

Andreas Wolter

Christian Geissler

Irmgard Escher-Poeppel

Adolf Koller

Thomas Ort

Ottmar Geitner

Bernd Rakow

Mehran Pour Mousavi

Stephan Brandl

A semiconductor flip-chip package includes a substrate having a first main face, a second main face opposite to the first main face, and one or more conductive structures disposed on the first main face, one or more pillars disposed on at least one of the conductive structures, a semiconductor die having one or more contact pads on a main face thereof, the semiconductor die being connected to the substrate so that at least one of the contact pads is connected with one of the pillars, and an encapsulant disposed on the substrate and the semiconductor die.

Method for fabricating a semiconductor flip-chip package

An electronic device comprising a semiconductor package having a first main surface region and a second main surface region and comprising a semiconductor chip comprising at least one chip pad in the second main surface region and a connector block comprising at least one first electrically conductive through connection and at least one second electrically conductive through connection extending with different cross-sectional areas between the first main surface region and the second main surface region and being arranged side-by-side with the semiconductor chip.

Connector block with two sorts of through connections, and electronic device comprising a connector block

A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

Workpiece with semiconductor chips, semiconductor device and method for producing a workpiece with semiconductor chips

In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.

Semiconductor packages with integrated antenna and method of forming thereof

A semiconductor device and manufacturing method. One embodiment provides a semiconductor chip. An encapsulating material covers the semiconductor chip. A metal layer is over the semiconductor chip and the encapsulating material. At least one of a voltage generating unit and a display unit are rigidly attached to at least one of the encapsulating material and the metal layer.

Semiconductor device and manufacturing method

A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.

Method and system for routing electrical connections of semiconductor chips

Structure for electrostatic discharge in embedded wafer level packages

An electronic assembly is disclosed. One embodiment includes at least one semiconductor chip and a package structure embedding the semiconductor chip. The package structure includes at least one conducting line extending into an area of the package structure outside of the outline of the chip. The electronic assembly further includes a substrate embedding the package structure.

Embedded chip package

A method of manufacturing a stacked die module includes applying a plurality of stacked die structures to a carrier. Each stacked die structure includes a first semiconductor die applied to the carrier and a second semiconductor die stacked over the first semiconductor die. The second semiconductor die has a larger lateral surface area than the first semiconductor die. A dam is applied around each of the stacked die structures, thereby forming an enclosed cavity for each of the stacked die structures. The enclosed cavity for each stacked die structure surrounds the first semiconductor die of the stacked die structure.

Method of manufacturing a stacked die module

A semiconductor module includes components in a plastic casing. The semiconductor module includes a plastic package molding compound and a semiconductor chip. Also provided in the module are a first principal surface including an upper side of the plastic package molding compound and at least one active upper side of the semiconductor chip, a second principal surface including a back side of the plastic package molding compound, and a multilayered conductor track structure disposed on the first principal surface and a second metal layer disposed on the second principal surface.

Semiconductor module including components in plastic casing

Stacked semiconductor chips are disclosed. One embodiment provides an array of first semiconductor chips, covering the array of the first semiconductor chips with a mold material, and placing an array of second semiconductor chips over the array of the first semiconductor chips. The thicknesses of the second semiconductor chips is reduced. The array of the first semiconductor chips are singulated by dividing the mold material.

Stacked semiconductor chips

One aspect relates to a method for singulating semiconductor wafers to form semiconductor chips. A semiconductor wafer is provided with semiconductor chip positions arranged in rows and columns, rectilinear separating tracks being arranged between the positions. Crystallographic strains are induced into the region of the separating tracks. This is followed by a laser ablation along the separating tracks, the semiconductor wafer being separated into individual semiconductor chips.

Growing community of inventors

Wuppertal, Germany

Klaus Pressel