Infineon Technologies Ag

Qimonda Ag

Qimonda North America Corporation

Klaus Nierle

Martin Versen

KoonHee Lee

Hoon Ryu

Ryan Patterson

Oliver Kiehl

Joerg Kliewer

Ernst Stahl

Peter W Schneider

A method for manufacturing a multiple-chip memory device includes making a volatile memory element on a semiconductor substrate, examining the volatile memory element for one or more initial errors, correcting the one or more initial errors on the semiconductor substrate, incorporating the volatile memory element into the multiple-chip memory device, and incorporating a non-volatile memory element into the multiple-chip memory device. The volatile memory element is examined for one or more secondary errors, after incorporating the volatile memory element and the non-volatile memory element into the multiple-chip memory device. Repair information is stored in a non-volatile memory element, the repair information identifying the one or more secondary errors.

Apparatus and method for manufacturing a multiple-chip memory device with multi-stage testing

A multiple-chip memory device, comprising: a volatile memory element configured to store a plurality of bits of information, and later access the plurality of bits of information; a non-volatile memory element configured to store initial repair information identifying one or more errors in the volatile memory element; and a master memory controller configured to read the initial repair information, and to provide processed repair information and volatile memory control signals to the volatile memory element, wherein the volatile memory element is configured to store and access the plurality of bits of information based on the processed repair information and logical address information.

System and method for addressing errors in a multiple-chip memory device

Method and system for testing an integrated circuit

An embodiment of the present invention receives a data signal and at least one data shift signal that facilitates adjustment of the data signal and produces a resulting data signal with a data rate greater than a data rate of the data signal.

Method and apparatus for increasing clock frequency and data rate for semiconductor devices

A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed. Data is then written to and read from memory locations which are accessed by delayed address signals, and a determination is made as to whether the data read from any memory location does not correspond with the data written to such memory location.

Test mode method and apparatus for internal memory timing signals

Methods and apparatus for accessing serial presence detect data are provided. For some embodiments, serial presence detect logic is incorporated in memory devices, eliminating the need for a separate serial presence detect component.

Serial presence detect functionality on memory component

A technique to simplify the cost and complexity of performing a full wafer test or probe of semiconductor wafers. A probe card connection layer is disposed on a surface of the wafer. The probe card connection layer comprises a plurality of probe contact connection points on a top surface of the probe card connection layer and a plurality of conductive traces on a bottom surface of the probe card connection layer. Each conductive trace is electrically connected to a corresponding probe contact connection point and electrically connected to a similar function connection point on each of a plurality of chips. Each conductive trace carries a test signal supplied to a corresponding probe contact connection point to the similar function connection points of the chips to which it is connected. A test signal can be delivered from a probe card device to multiple chips in the wafer nearly simultaneously from one probe card contact, thus greatly reducing the number of contacts required on the probe card and reducing the time required to test each chip on the wafer.

Method for full wafer contact probing, wafer design and probe card device with reduced probe contacts

DRAM memory device () comprising at least one array of memory cells (), each memory cell () being connected to a bit line (BL) and a word line (WL), each of said bit lines (BL) being connected to a sense amplifier and a pre-charge circuit (); a controllable active-current generator () for providing power to the sense amplifiers and pre-charge circuits () for a time interval that is limited by a time at which a command for a read or write access is applied to the DRAM memory device () and an assigned switching time; a controllable standby-current generator () for providing power to the sense amplifiers and pre-charge circuits () after the switching time; a control circuit () for receiving external data, address and control signals (C, A, D) and for controlling the active-current generator () and the standby-current generator (); wherein the control circuit () is adapted to control the time for switching the respective power generator () to the sense amplifiers and to the pre-charge circuits () subject to an external test mode signal for reducing the overall testing time in a test of the serviceability of the bit lines (BL), sense amplifiers and pre-charge circuits ().

Method for testing the serviceability of bit lines in a DRAM memory device

A semiconductor memory is provided which is operable in at least a test mode. Such semiconductor memory includes a memory array, the memory array including a plurality of memory cells which are accessible through a plurality of respective wordlines and a plurality of respective bitlines. A row decoder driver is operable to activate one wordline of the plurality of wordlines at a first point in time that is determined in relation to a first signal and to deactivate the wordline at a second point in time that is determined in relation to a second signal. The semiconductor memory further includes a precharge circuit which is operable to precharge the bitline at a third point in time, the third point in time occurring no sooner than the second point in time. A variable length delay circuit is operable to output the second signal at a delayed timing after the first signal and delayed in relation to the first signal, the delayed timing having a controllably variable length.

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Essex Junction, VT, United States of America

Klaus Nierle