Sap Ag

Sap Se

Klaus Kretzschmar

Nobuyoshi Mori

Markus Eble

Arne Harren

Maciej Kabala

Tobias Elfner

Philipp Becker

Ivan Galkin

Vaidas Gasiunas

Matthias Liedtke

Torsten Ihben

Implementations of the present disclosure include receiving object-oriented source code including a set of kernel functions and a set of invocations, each invocation invoking one or more kernel functions, each kernel function being marked within the source code as being GPU-enabled and referencing a information object and a grid configuration object, the grid information object defining a number of threads for executing the kernel function within the GPU, and the grid configuration object defining a configuration of threads for executing the kernel function within the GPU, the source code capable of being compiled to one of binary code that is executable by a CPU and binary code that is executable by a GPU without modification, compiling the object-oriented source code to provide binary code that is executable by a GPU, and executing the binary code using the GPU to execute the kernel function within an in-memory database system.

Object oriented programming model for graphics processing units (GPUS)

Approaches to memory management and synchronization are described relating to provision of highly robust and highly available servers that can serve multiple requests in parallel. Programming objects can be analyzed at design time by comparison to predefined patterns to identify a set of requirements and rules that must be followed to ensure that all part of a program cooperate. In highly complex programming environments, enforcement of such rules for a program as a whole can be quite difficult. As such, analysis of compliance can desirably occur at a programming object level.

Approach for modularized sychronization and memory management

According to some embodiments, a system and method for determining a value for an error code for a program operation; determining whether the operation supports postponing a determination of an occurrence of an error for the operation; proceeding to evaluate a next operation in an instance the operation does support postponing the determination of an occurrence of an error for the operation; and checking the error code for the operation in an instance the operation does not support postponing the determination of an occurrence of an error for the operation.

Method and system for postponed error code checks

The invention comprises methods for manipulating floating point numbers on a microprocessor where the numbers are sortable. That is, the numbers obey lexicographical ordering. Hence, the numbers may be quickly compared using bit-wise comparison functions such as memcmp( ). Conversion may result in a sortable floating point number in the form of a sign, leading bits of the exponent, and sets of digit triples in the form of declets (sets of 10 bits). In a variable-length version, numbers may be compressed by storing the number of trailing zero declets in lieu of storing the zero declets themselves.

Sortable floating point numbers

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Angelbachtal, Germany

Klaus Kretzschmar