Infineon Technologies Ag

Qimonda Ag

Qimonda Flash Gmbh

Klaus Knobloch

Robert Strenz

Achim Gratz

Franz Schuler

Robert Allinger

Michael Specht

Dirk Manger

Detlev Richter

Christian Peters

Mayk Roehrich

Karl Hofmann

Snezana Jenei

Steffen Meyer

Christoph Friederich

Gert Koebernik

Jan Gutsche

Eike Ruttkowski

Joseph Willer

Kenny Oisin

Holger Moeller

Doris Keitel Schulz

A method for applying a magnetic shielding layer to a substrate is provided, wherein a first magnetic shielding layer is adhered to a first surface of the substrate. A first film layer is adhered to the first magnetic shielding layer and the first magnetic shielding layer is more adherent to the first surface than the film layer to the first magnetic shielding layer.

Method for applying magnetic shielding layer, method for manufacturing a die, die and system

A memory having an array of perpendicular spin-transfer torque (STT) magnetic random access memory (MRAM) cells, wherein each cell has a magnetic layer stack. A magnetic shield disposed between the cells and having a minimum height of at least the height of the magnetic layer stacks.

Magnetic shielding of perpendicular STT-MRAM

A method of forming a memory includes forming a first electrode and a second electrode within a first layer over a semiconductor substrate, forming a resistive-switching memory element and an antifuse element over the first layer, wherein the resistive-switching memory element includes a metal oxide layer and is electrically contacting the first electrode, wherein the metal oxide layer has a first thickness and a forming voltage that corresponds to the first thickness, wherein the antifuse element includes a dielectric layer and is electrically contacting the second electrode, and wherein the dielectric layer has a second thickness that is less than the first thickness and a dielectric breakdown voltage that is less than the forming voltage, and forming a third electrode and a fourth electrode within a second layer over the resistive-switching memory element and the antifuse element, wherein the third electrode is electrically contacting the resistive-switching memory element and the fourth electrode is electrically contacting the antifuse element.

Method of forming a memory and method of forming a memory array

A memory includes a first electrode and a second electrode formed within a first layer and includes a third electrode and a fourth electrode formed within a second layer. The memory includes a resistive-switching memory element and an antifuse element. The resistive-switching memory element includes a metal oxide layer and is disposed between the first electrode and the third electrode. The metal oxide layer has a first thickness and a forming voltage that corresponds to the first thickness. The antifuse element includes a dielectric layer and is disposed between the second electrode and the fourth electrode. The dielectric layer has a second thickness that is less than the first thickness and a dielectric breakdown voltage that is less than the forming voltage.

Memory

A transistor arrangement includes a switch transistor and a sense transistor. The switch transistor includes a charge storing structure and a control structure. The sense transistor includes a charge storing structure, a control structure and a select structure. The charge storing structure of the switch transistor is electrically connected to the charge storing structure of the sense transistor. The sense transistor is configured such that the select structure and the control structure of the sense transistor may be electrically controlled independently from one another.

Transistor arrangement and integrated circuit

Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.

Integrated circuits; methods for manufacturing an integrated circuit; memory modules; computing systems

An explanation is given of, inter alia, a circuit arrangement containing a trench which penetrates through a charge-storing layer () and a doped semiconductor layer (). The trench simultaneously fulfils a multiplicity of functions, namely an insulating function between adjacent components, the patterning of the charge-storing layer and also the subdivision of doping layers of the semiconductor layer ().

Semiconductor circuit arrangement with trench isolation and fabrication method

A flash memory cell can be read by selecting a local bit line. A read potential is applied to a memory cell transistor associated with the local bit line thereby generating a capacitive loading of the local bit line. The capacitive loading depends upon a magnitude of charge stored on a floating gate of the memory cell transistor. The capacitive loading of the local bit line can then be assessed to determine a state of the memory cell transistor, the state being related to the magnitude of the charge stored on the floating gate.

Method for reading Uniform Channel Program (UCP) flash memory cells

Growing community of inventors

Dresden, Germany

Klaus Knobloch