Intel Corporation

Klaus J Ruff

Kuljit Singh Bains

James A McCall

George Vergis

David N Shykind

Suneeta Sah

Santanu Chaudhuri

Howard S David

John F Zumkehr

John L Bryan

A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

Accessing data stored in a command/address register device

A method, system and apparatus to self-determine equalization parameters for a channel. An initiator sends an equalization insensitive signal (EIS) to a responder on channel to be equalized and begins a count. A responder responds with an EIS. When the initiator receives the response EIS the count is terminated. The count, which constitutes a measure of delay in the channel, may be used to determine desirable equalization parameters for the channel.

Adaptive delay base loss equalization

Link initialization techniques to decouple the read training from the write training. Read training may be accomplished in a robust manner before write training is performed. These techniques may provide significantly improved link initialization times. A user-programmable register within a dynamic random access memory (DRAM) module may be utilized by the decoupled read training and write training processes. The decoupling may result in shorter and more robust training segments that may support faster training and/or increased link speeds.

Memory link initialization

A method includes detecting a change in temperature in an integrated circuit that is coupled to a differential communication link, and responding to the detected change in temperature by initiating a retraining process for the differential communication link.

Initiation of differential link retraining upon temperature excursion

A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e.g., DDR SDRAM) includes conducting an iterative two-dimensional data eye search for optimizing the delay of the source synchronous clock reference signal (e.g., DQS). Embodiments of the present invention are directed to tuning the delay for each device for the optimal margin in two dimensions: maximize the distance from the data eye walls and maximize the noise margin on the interface. An iterative data eye search is performed while varying the DQS delay timing and noise margin.

Two dimensional data eye centering for source synchronous data transfers

A method of controlling a slew rate includes applying a resistive load to a bus corresponding to the number of logic components in a computer. The number of logic components within the computer is varied by either adding or removing a logic component. A second resistive load is selected to be applied to the bus after the number of logic circuits in the computer has been changed. The selection of a second resistance enables the slew rate to be controlled when the number of components change.

Method for topology dependent slew rate control

A slew rate control circuit of a bus includes two connection devices that are adapted to be coupled to two voltage supplies. The connection devices are connected to the bus by a select terminal of a signal application device. The signal application device has first and second positions which apply first and second amounts of resistance to the bus depending on the voltage on the select terminal. If an expansion board is adapted to be coupled to the bus, a different voltage is applied on the select terminal. A method for controlling a slew rate includes applying a resistive load to a bus corresponding to the number of logic circuits in a computer system. The number of logic circuits within the computer is varied by either adding or removing a logic circuit. A second resistive load is selected to be applied to the bus after the number of logic circuits in the computer system has been varied. The selection of a second resistance enables the amount of slew rate to be reduced.

Growing community of inventors

Beaverton, OR, United States of America

Klaus J Ruff