Infineon Technologies Ag

Qimonda Ag

Qimonda North America Corporation

Infineon Technologies North America Corp.

International Business Machines Corporation

Siemens Aktiengesellschaft

Klaus Hummler

Wayne Frederick Ellis

Oliver Kiehl

Josef Schnell

Lee Ward Collins

Octavian Beldiman

Jung Pill Kim

Jong Hoon Oh

Ramachandra Divakaruni

Arnd Scholz

Jong-Hoon Oh

Wolfgang Hokenmaier

Ernest N Levine

Norbert Arnold

Khaled Fekih-Romdhane

Vincent Acierno

Daniele Casarotto

Jung Pil Kim

Rainer Weiland

Richard Lewison

A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.

Multi-chip package with interconnected stacked chips

A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors.

Memory refresh system and method

Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP.

Method and structure of expanding, upgrading, or fixing multi-chip package

Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew.

Method and apparatus for synchronizing memory enabled systems with master-slave architecture

A method of routing signals within a semiconductor memory device includes providing a semiconductor wafer having a top surface with a center portion, an edge portion and wafer bond pads at the center portion. A redistribution layer is provided on the top surface of the semiconductor wafer. The method includes redistributing signals from the wafer bond pads to redistribution edge pads utilizing the redistribution layer, and routing signals from the semiconductor wafer up to the redistribution layer and routing these signals back down to the semiconductor wafer.

Signal routing on redistribution layer

Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory device, while command decoding logic of the second memory device is bypassed.

Method and apparatus for implementing memory enabled systems using master-slave architecture

The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least one non-volatile memory chip, and at least one fail signature register for storing fail signature data related to memory errors detected in the MCP. The controller can poll the fail signature register for fail signature data related to memory errors stored therein. Upon detection of fail signature data, the controller can store the fail signature data on a fail signature register located on a non-volatile memory.

Self-diagnostic scheme for detecting errors

Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage.

Structure to share internally generated voltages between chips in MCP

A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory.

Memory configured on a common substrate

A memory includes a sense amplifier segment and a plurality of word lines including a first transfer word line and a second transfer word line complementary to the first transfer word line. The memory includes a plurality of bit lines coupled to the sense amplifier segment and a memory cell located at each cross point of each word line and each bit line. The first transfer word line and the second transfer word line are adapted for simultaneously inverting data bit values stored in memory cells along a failed word line to correct a parity error during self refresh.

Memory having parity error correction

A memory includes a sense amplifier segment and a plurality of word lines including a spare word line, a first transfer word line, and a second transfer word line complementary to the first transfer word line. The memory includes a plurality of bit lines coupled to the sense amplifier segment and a memory cell located at each cross point of each word line and each bit line. The first transfer word line and the second transfer word line are adapted for simultaneously inverting data bit values stored in memory cells along a failed word line to correct a parity error during self refresh.

Trim codes are determined for semiconductor devices under test (DUTs), wherein the trim codes correspond to voltage or current reference value adjustments that cause the DUTs to generate desired voltage or current reference values. The technique involves supplying respective trim codes simultaneously to the DUTs to cause them to generate trimmed analog voltage or current references, simultaneously feeding a test analog voltage or current reference having a preselected reference value to the DUTs, and for each DUT, comparing the value of the test analog reference to the values of the trimmed analog references to ascertain the crossing of the value of the test analog reference by the values of the trimmed references, whereby for each DUT the trim code corresponding to the value of the trimmed analog voltage or current reference immediately above or below the crossing is established as the preferred trim code to be used for that DUT.

Method and system for trimming voltage or current references

An inversion device includes a differential amplifier having first and second input lines, and a controller coupled to the first and second input lines to selectively and individually decouple the first and second input lines from the differential amplifier.

Data inversion device and method

A semiconductor integrated circuit memory device is repaired by receiving an externally-supplied signal containing failure information that identifies at least row or column of memory cells in the memory device that has a failure. The externally-supplied signal contains failure information derived from error correction or other failure logs. The failure information is stored in the memory device and used for comparison against an incoming memory request. If a match is detected between the failure address information and the incoming memory request, then a redundant row or column is used for the memory access request. The repair feature may be performed during power up of the memory device, or normal operation may interrupted by a repair command that places the memory device in a standby mode for the repair.

Repair of semiconductor memory device via external command

A semiconductor wafer has a dielectric layer, a metal last layer, a passivation layer, and a redistribution layer. The metal last layer is formed over the dielectric layer, and the metal last layer has first and second locations that are spaced apart from each other. The passivation layer is formed over the metal last layer. The redistribution layer is formed over the passivation layer. The redistribution layer has a signal routing wire coupled to the first location of the metal last layer and to the second location of the metal last layer.

Growing community of inventors

Apex, NC, United States of America

Klaus Hummler