International Business Machines Corporation

Klaus Heuber

Siegfried K Wiedmann

Knut K Najmann

Wilfried Klein

Rolf Remshardt

Erich Klink

Volker Rudolph

Friedrich C Wernicke

Horst H Berger

Klaus Tertel

A method of and a circuit arrangement for reading an integrated MTL(I.sup.2 L) store are described, wherein prior to or during a read operation, line capacities are discharged and in addition to the word line drivers and the bit line drivers, a read/write circuit is provided. Simultaneously with the selection of a word line (WL) or with a slight time delay (t1), two identical current sources (IRD0) are connected by means of two switches (S0 and S1) to the relevant bit lines (B0 and B1). As a result, the two injectors of the two bit line PNP transistors (T1 and T4) are supplied with the same currents. In a second phase (t2), the current sources (IRD0) are switched off so that the duration of the second time phase (t2) considerably exceeds the storage time constant (.tau.e) of the bit line PNP transistor (T4) connected to the switched 'OFF' NPN transistor (T3) of a cell. The effective storage time constant (.tau.SAT) of the bit line PNP transistor (T1 ), connected to the switched on NPN cell transistor (T2), considerably exceeds the storage time constant (.tau.e). As a result of the different time constants (.tau.e and .tau.SAT), the two storage charges (Q1 and Q4) are discharged at different rates during the third phase (t3), thus generating a very fast and high output signal (.DELTA.VBL=VS).

Method of and circuit arrangement for reading an integrated

Disclosed is a restore circuit for restoring an integrated semiconductor storage array having storage cells consisting of bipolar transistors. The restore circuit includes a reference voltage generator, an impedance converter, and switches to connect the reference voltage generator and the impedance converter to the storage array. The reference voltage generating circuit includes a current source and at least one reference storage cell identical in construction to the storage cells of the array. The reference voltage generating circuit provides a reference voltage to the impedance converter which supplies a second reference voltage to the array at a greatly reduced impedance. The equivalent circuit of the storage cells is that of a capacitor in parallel with a diode. Thus, the impedance converter provides an initial surge of capacitive current which restores the cells, followed by a standby current which is a function of the diode characteristics of the cell equivalent circuit.

Restore circuit for a semiconductor storage

A method and arrangement is provided for selecting and discharging a pair of bit lines of a plurality of charged pairs of bit lines of a memory circuit having cells of the merged transistor logic type. A selected pair of bit lines is discharged through a selected cell coupled to the selected pair of bit lines while simultaneously the remaining or non-selected pairs of bit lines are discharged through a common switch into non-selected word lines.

Method and circuit arrangement for discharging bit line capacitances of

Disclosed is a simulated storage cell structure for use as a reference voltage generator in a semiconductor store fabricated in Merged Transistor Logic (MTL) technology. The simulated storage cell structure includes n elongated regions of P-type diffusion arranged in parallel to each other in an N-type trough of semiconductor material. The elongated P-type regions are alternately designed as collector and Injector strips.

Storage cell simulation for generating a reference voltage for

In integrated semiconductor memory cell arrangements, particularly integrated semiconductor memory cell arrangements using merged transistor logic configurations, line capacitances are discharged before accessing to reduce access time and power consumption. Individual bit line transistor switching means are coupled to each bit line to provide a discharge path for the line capacitances associated therewith. Common transistor switching means are coupled to each individual bit line transistor switching means to commonly discharge the individual discharge currents received from each individual bit line transistor switching means. Individual word line transistor switching means are also connected to respective word lines to distribute the current passing through the common transistor switching means to the respective word lines. The discharge circuit arrangement permits minimum-area bit line and word line transistor switching means.

Method and circuit arrangement for controlling an integrated

The invention relates to a monolithically integrated semiconductor arrangement with at least one integrated injection logic (I.sup.2 L) structure including an injection zone and an inverting transistor, the injection zone, and lateral thereto, the transistor base zone of a same first conductivity type being arranged in a semiconductor layer of a second conductivity type, which forms the emitter zone of the transistor, the transistor being completed by a collector zone of the second conductivity type, which is formed in the base zone, and the I.sup.2 L structure being surrounded at least partly by a separating zone introduced at a predetermined spacing into the semiconductor layer. The injection zone and the transistor base zone in the region of their edges facing each other are extended up to or into the separating zone, while in the region of their remaining edges they are spaced therefrom at the predetermined distance. The invention further relates to a storage arrangement having storage cells including two such I.sup.2 L structures each which are cross-coupled in the manner of a flip-flop.

IIL With partially spaced collars

A memory storage system which utilizes semiconductor storage cells comprised of cross-coupled bipolar transistors arranged in a memory system array with an error reference circuit and a standby reference circuit that is controlled by a clock signal. The standby reference circuit and the error reference circuit are both coupled to the bit lines and selectively control a restore circuit that maintains, in the standby state, a selected potential on the bit lines such that short access times are realized and current is prevented from flowing into unselected cells when adjacent defective cells are being read or written.

Memory storage array with restore circuit

The invention relates to a circuit arrangement for operating the read/write cycles of an integrated semiconductor memory storage system whose storage cells consist of flip flops with bipolar switching transistors, Schottky diodes as read/write elements coupling the cell to the bit lines, and high-resistivity resistors, or transistors controlled as current sources, as load elements, in several phases. This is accomplished through coupling the storage cell to both read/write circuits and restore/recovery circuits via the bit lines and by selective pulsing of the cell with the read/write circuits and the restore/recovery circuits. This permits high speed, low operating current, large scale memory systems to be built.

Circuit arrangement for operating a semiconductor memory system

An improved method of operating a monolithic memory together with novel and efficient circuitry for practicing said improved method is disclosed. In a bipolar transistor store, or monolithic memory, in accordance with the invention, a very low current (first level) flows from the load elements to the internal cell nodes in the stand-by mode. During the initial portion of a read cycle, current flows from the bit lines to the cell nodes, in addition to the stand-by current (second level). In the recovery period of the read cycle or write cycle a short pulse is added to the stand-by current (third level), thereby reducing the recovery time. The practice of the invention provides a monolithic memory having minimal power requirements and a substantially reduced cycle time.

Read/write speed up circuit for integrated data memories

This teaches a sense circuit for an integrated memory storage system in which the storage cell output is detected by a differential amplifier, controlling a flip-flop, serving as a latch, having load elements which also function as the load elements of the latch to ensure an optimum power and speed product. The latch can be coupled to an output driver circuit through a current switch which shares common elements with the latch to assure that the latch remains symmetrical even when used with an output driver having asymmetrical control.

Sense circuit for memory storage system

This describes an integrated semiconductor structure having an epitaxial semiconductor layer, divided into regions by isolation zones and containing active and passive semiconductor devices, of a first conductivity type on a substrate of the opposite second conductivity type. A reference potential and first and second supply voltages are applied to the structure. An additional isolated transistor, in accordance with this invention prevents an unlimited current flow, via the chip isolation junction, from one voltage supply to the other when the power-on sequence for both voltages is undefined. The base of this additional transistor is connected to one of the voltages via an integrated resistor while the other voltage is connected to the emitter and the collector is connected to the substrate via the isolation zone. Thus, the isolation junction can never become forward biased. In addition, this arrangement ensures that the substrate potential is independent of the rate of the above-mentioned substrate current, and perfect isolation is guaranteed under all conditions.

Integrated semiconductor structure with means to prevent unlimited

Modern bipolar cross coupled memory cells for high density arrays use diodes as coupling elements from the cell to the bit lines. The write operation of these cells requires a high amount of current if the current gain of the cell transistors is high. The time required to perform a write operation is prolonged significantly due to the inherent capacitors in the cell known as the Miller effect. The described circuit completely eliminates the Miller effect during the write operation and makes the required write current completely independent of the current gain of the cell transistors. In the present invention this is accomplished by dropping the word line of such a cell from a stand-by potential to a select potential, so that the inner cell nodes are equally discharged, without disturbing the state of the cell, after which the word line is pulsed up to an intermediate potential between the select potential and the stand-by potential.

Write speed-up circuit for integrated data memories

A method and circuit arrangement for operating an information store, in particular a monolithic information store, whose storage cells and address circuits comprise bipolar transistors which are not continuously subjected to full power. The monolithic information store is readily fabricated by known planar process technology, has increased density, has reduced read/write times, reduced cycle time, and reduced power dissipation.

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Boeblingen, Germany

Klaus Heuber