Infineon Technologies Ag

International Business Machines Corporation

Infineon Technologies North America Corp.

Klaus Herold

Sajan Marokkey

Erdem Kaltalioglu

Martin Ostermayr

Sun-Oo Kim

Jenny Lian

O Seo Park

Roberto Schiwon

Matthew Earl Colburn

Scott David Halle

Henning Haffner

Alois Gutmann

Scott Marshall Mansfield

Allen H Gabor

Haoren Zhuang

Uwe Paul Schroeder

Chandrasekhar Sarma

Helen Wang

Ian P Stobert

Zachary Baum

Azalia A Krasnoperova

Jason E Meiring

Paul Uwe Schroeder

Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a semiconductor device includes a plurality of contacts disposed over a substrate, the plurality of contacts being disposed as rows and columns on an orthogonal grid, each row of the plurality of contacts is spaced from an neighboring row of the plurality of contacts by a first distance, and each column of the plurality of contacts is spaced from an neighboring column of the plurality of contacts by a second distance.

Methods for forming contacts in semiconductor devices

Systems and methods of optical proximity correction are disclosed. A preferred embodiment comprises a method of determining optical proximity correction, which includes providing a design for a lithography mask. The design comprises a layout for a material layer of a semiconductor device. A predicted wafer image producible by the design for the lithography mask is calculated, and an amount of error between a target image and the calculated predicted wafer image is measured over a plurality of pixels of the predicted wafer image. The plurality of pixels comprises a plurality of different sizes.

Methods of optical proximity correction

Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features.

Semiconductor devices and methods of manufacturing thereof

Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.

Integrated circuits and methods of design and manufacture thereof

Embodiments of the present invention provide a method for making mask shape adjustment The method includes creating a first mask shape; identifying one or more mask segments of the first mask shape as candidate mask segments of needing segment adjustment; applying an optical proximity correction (OPC) process to the first mask shape, the OPC process identifying at least one of the candidate mask segments as a constrained mask segment; applying a rotational adjustment to the constrained mask segment; and creating a second mask shape having the constrained mask segment being rotationally adjusted. A system and a machine-readable medium for performing the above method are also provided.

Adjustment of mask shapes for improving printability of dense integrated circuit layout

Lithography masks and methods of lithography for manufacturing semiconductor devices are disclosed. Forbidden pitches are circumvented by dividing a main feature into a set of two or more sub-features. The sum of the widths of the sub-features and the spaces between the sub-features is substantially equal to the width of the main feature. The set of two or more sub-features comprise a plurality of different distances between an adjacent set of two or more sub-features. At least one of the plurality of distances comprises a pitch that is resolvable by the lithography system, resulting in increased resolution for the main features, improved critical dimension (CD) control, and increased process windows.

Lithography masks and methods

Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a method of manufacturing a semiconductor device includes a exposing a first photo resist layer using a first light beam thereby forming first features. The first exposure is performed by the first light beam passing through a first dipole illuminator and then a first mask. A dipole axis of the first dipole illuminator is oriented in a first direction. After exposing the first photo resist layer, forming second features using a second exposure with a second light beam. The second exposure is performed by the second light beam passing through a second dipole illuminator and then a second mask. A dipole axis of the second dipole illuminator is oriented in a second direction. The first direction and the second direction are not perpendicular. The first and the second features comprise a pattern for forming contact holes.

Gridded contacts in semiconductor devices

Methods of patterning features of semiconductor devices and methods of processing and fabricating semiconductor devices are disclosed. In one embodiment, a method of processing a semiconductor device includes forming first sidewall spacers on a first hard mask, removing the first hard mask, and forming a first material layer over the first sidewall spacers. A second hard mask is formed over the first material layer and the first sidewall spacers. Second sidewall spacers are formed on the second hard mask, and the second hard mask is removed. At least the first sidewall spacers are patterned using the second sidewall spacers as a mask.

Feature patterning methods

Semiconductor devices having conductive lines with extended ends and methods of extending conductive line ends by a variable distance are disclosed. An end of a first conductive feature of an interconnect structure is extended by a first distance, and an end of a second conductive feature of the interconnect structure is extended by a second distance, the second distance being different than the first distance. Ends of conductive features that are positioned close to adjacent conductive features are preferably not extended.

Methods of forming an interconnect structure

Memory card with connecting portions for connection to an adapter

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Poughquag, NY, United States of America

Klaus Herold