Temic Telefunken Microelectronic Gmbh

Klaus Graff

Wolfgang Arndt

Petra Heim

Alfons Hamberger

Werner Zurek

A process for manufacturing a silicon semiconductor device having a reduced surface recombination velocity of charge carriers within a silicon wafer includes forming a plurality of semiconductor zones in the surface; reducing surface recombination velocity of charge carriers within the silicon wafer by maintaining temperature below 100&deg; C. while sequentially performing the steps of cleaning the surface to remove oxide; drying the surface by blowing a non-oxidizing gas thereon; directly applying a layer of lacquer onto the surface at a temperature below 100&deg; C.; and drying the layer of lacquer at a temperature below 100&deg; C. to generate an electrically non-conducting layer and reduce the surface recombination velocity of charge carriers within the silicon wafer in which the layer of lacquer contains halogen in a concentration of more than 0.1 volume %; and forming at least one conducting structure on the surface of the layer of lacquer.

Process for manufacturing a silicon semiconductor device having a reduced surface recombination velocity

The reduction of surface recombination is required for the manufacture of electronic devices made of silicon as well as for the application of various measurements and analytical methods for determining the purity of silicon. According to this invention, a process will be described for applying a laquer layer to the surface of silicon wafers, wherby the surface recombination velocity will be reduced to a value below 100 cm/s.

Process for reducing the surface recombination speed in silicon

A method is described for manufacturing semiconductor components with short switching time, having a weakly doped semiconductor area in contact with a PN junction. In order to obtain an inhomogeneous impurity distribution in the axial direction of the semiconductor array, the following process steps are implemented: a) gold impurities are placed in the semiconductor array and homogeneously distributed there in a first diffusion process, b) a layer comprising a 3d transition metal affecting the charge carrier lifetime is deposited onto that surface side of the semiconductor array having a shorter distance from the weakly doped semiconductor area, c) the 3d transition metal is incorporated into the semiconductor array by a second diffusion process and is inhomogeneously distributed there, such that an impurity surplus is generated in a partial area of the weakly doped semiconductor area in the vicinity of the PN junction.

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Heilbronn, Germany

Klaus Graff