Micron Technology Incorporated

Newport Fab, LLC

Applied Materials, Inc.

Sandisk 3D LLC

Other

Sandisk Technologies Inc.

Sandisk Corporation

Conexant Systems, Inc.

Pdf Solutions, Incorporated

Newport Fab, LLC Dba Jazz Semiconductor

Manfred R. Kuehnle

Klaus Florian Schuegraf

Randhir P S Thakur

Randhir P Thakur

Greg D U'ren

Pierre C Fazan

Marco Racanelli

Scott Jeffrey DeBoer

Aftab A Ahmad

Amol M Kalburge

Kevin Q Yin

Tyler A Lowrey

Bob Carstensen

Deepak Chandra Sekar

John K Zahurak

Tuan Duc Pham

Thomas Arthur Figura

Scott J Deboer

Carl Powell

Roy E Scheuerlein

Masaaki Higashitani

Michael Robert Rice

Nima Mokhlesi

Manfred R Kuehnle

Ronald Allen Weimer

April Dawn Schricker

Nanseng Jeng

Mike P Violette

Seshadri Ramaswami

Claes H Bjorkman

Mohsen Salek

Xiying Chen

Sanghyun Lee

Fernando Gonzales

Pankaj N Joshi

David L Chapek

Masato Horiike

Keiichi Isono

Raghuveer S Makala

Dmitry Lubomirsky

Thorsten B Lill

Matthew S Rogers

Peter J Zampardi

Joseph R Johnson

Peter M Asbeck

Hermann Statz

John Gerling

Paul Kempf

Robert K Carstensen

Arno K Hagenlocher

Christoph Dolainsky

Hendrik Schneider

Depak C Sekar

Arjun KarRoy

Dong Kyu Lee

Arno Hagenlocher

Kelvin Yih-Yuh Doong

Huan Tsung Huang

Disclosed is a system and method for performing direct memory characterization of memory cells in a memory array using peripheral transistors. A memory array is fabricated using a mask layer defining routing for a set of first stage periphery transistors electrically connected to the word lines of the memory array. A revised mask is used for defining a different routing for a set of second stage periphery transistors including different characteristics than the first stage periphery transistors. Testing is conducted by applying a simulated Erase signal to the nonvolatile memory cells and determining which cells are erased. Based on this test, certain characteristics of the first and/or second stage periphery transistors can be identified that provide improved conditions for the nonvolatile memory cells. A product chip can be manufactured using modified versions of the first stage periphery transistors that incorporate the characteristics that provide the improved condition(s).

Direct memory characterization using periphery transistors

A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.

Method and system for wafer level singulation

Apparatus for providing pulsed or continuous energy in a process chamber are provided herein. The apparatus may include a lamphead including a set of lamps, wherein the first set of lamps are not solid state light sources, and a set of solid state light sources disposed on the lamp head, to provide pulsed or continuous energy to the process chamber.

Solid state light source assisted processing

In some embodiments, an interlayer polysilicon dielectric cap disposed atop a substrate having a first floating gate, a second floating gate and an isolation layer disposed between the first floating gate and the second floating gate may include: a first nitrogen containing layer disposed atop an upper portion and sidewalls of the first floating gate and second floating gate; a first oxygen containing layer disposed atop the first nitrogen containing layer and an upper surface of the isolation layer; a second nitrogen containing layer disposed atop an upper portion and sidewalls of the first oxygen containing layer; and a second oxygen containing layer disposed atop the second nitrogen containing layer and an upper surface of the first oxygen containing layer.

Interlayer polysilicon dielectric cap and method of forming thereof

Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.

Integrated circuits with sidewall nitridation

Ultrathin material layers are plasma etched with an etch system configured for cryogenic cooling of a substrate to reduce the diffusion coefficients of foreign and intrinsic stop layer atoms (e.g., of the bombarded crystal lattice), and further configured for plasma pulsing to reduce the energy of the impinging ions with cryogenic wafer temperatures. Substrate temperatures of &#x2212;50&#xb0; C. or more are employed to reduce the susceptibility of a stop layer material to damage associated with ion impact. Ion energy is reduced to below the threshold where stop layer lattice atoms are displaced or ions are implanted into the bulk lattice. In embodiments, a plasma of an etchant gas having ion energies less than 10 eV are achieved through plasma pulsing, which when directed at the low temperature substrate may controllably etch ultra-thin material layers.

Pulsed plasma with low wafer temperature for ultra thin layer etches

Optimized electrodes for ReRAM memory cells and methods for forming the same are discloses. One aspect comprises forming a first electrode, forming a state change element in contact with the first electrode, treating the state change element, and forming a second electrode. Treating the state change element increases the barrier height at the interface between the second electrode and the state change element. Another aspect comprises forming a first electrode in a manner to deliberately establish a certain degree of amorphization in the first electrode, forming a state change element in contact with the first electrode. The degree of amorphization of the first electrode is either at least as great as the degree of amorphization of the state change element or no more than 5 percent less than the degree of amorphization of the state change element.

Optimized electrodes for Re-RAM

A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques are disclosed herein for achieving a high programming bandwidth while reducing the worst case current and/or power consumption.

Programming reversible resistance switching elements

Integrated circuit fabrication using sidewall nitridation processes

A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques are disclosed herein for achieving a high programming bandwidth while reducing the worst case current and/or power consumption. In one embodiment, a page mapping scheme is provided that programs multiple memory cells in parallel in a way that reduces the worst case current and/or power consumption.

Read disturb is reduced in non-volatile storage. In one aspect, when a read command is received from a host for reading a selected word line, a word line which is not selected for reading is randomly chosen and its storage elements are sensed to determine optimized read compare levels for reading the selected word line. Or, a refresh operation may be indicated for the entire block based on an error correction metric obtained in reading the storage elements of the chosen word line. This is useful especially when the selected word line is repeatedly selected for reading, exposing the other word lines to additional read disturb. In another aspect, when multiple data states are stored, one read compare level is obtained from sensing, e.g., from a threshold voltage distribution, and other read compare levels are derived from a formula.

Read disturb mitigation in non-volatile memory

A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the final isolation structure. Effective device isolation is achieved with a reduced trench depth by utilizing refilling dielectric materials having low dielectric constant.

Shallow trench isolation using low dielectric constant insulator

Growing community of inventors

Aliso Viejo, CA, United States of America

Klaus Florian Schuegraf