Infineon Technologies Ag

Siemens Aktiengesellschaft

Klaus Feldner

Albrecht Kieslich

Herbert Benzinger

Werner Graf

Virinder Grewal

Rainer F Schnabel

Elard Stein Von Kamienski

Kae-Horng Wang

Bernd M Vollmer

Hermann Sachse

Grit Schwalbe

A method for providing bitline contacts in a memory cell array includes a plurality of bitlines disposed in a first direction, the bitlines being covered by an isolating layer, a plurality of wordlines disposed in a second direction perpendicular to the first direction above the bitlines, and memory cells disposed at the points at which the bitlines and wordlines cross each other. According to a first aspect of the present invention, the isolating layer is removed from the bitlines at the portions that are not covered by the wordlines, whereas the areas between the bitlines remain unaffected. Alternatively, the isolating layer is removed from the whole cell array. Then, an electrical conductive material is provided on the exposed portions of the bitlines. The method is used to provide bitline contacts in a nitride read only memory (NROM&#x2122;) chip.

Method for providing bitline contacts in a memory cell array and a memory cell array having bitline contacts

A method for planarizing the surface of an isolating layer that is deposited on a semiconductor body is described. Zones where the isolating layer has a low level are covered with a block mask in order to be able to selectively etch zones of the isolating layer with a higher level.

Method for planarizing an isolating layer

A method for producing a semiconductor device having a first region with storage capacitors and a second region with at least one well surrounded by an insulation. The method creates both the storage capacitors and the insulation by forming trenches in the first region and at least one trench in the second region, and the trenches have a depth of at least 2 &mgr;m. The trenches in the first region are treated to provide first and second electrodes separated by a dielectric to form the capacitors and each trench in the second region provides an insulation which surrounds any wells in the second region.

Method for producing an insulation

An improved method of performing a dual damascene etch through a layer stack disposed above a substrate. The layer stack includes an underlying device layer and an insulating layer disposed above the underlying device layer. The method includes forming a trench in a top surface of the insulating layer such that the trench is positioned over the underlying device layer and separated therefrom by insulating material at a bottom of the trench. The method also includes, depositing flowable oxide over the top surface of the insulating layer and into the trench followed by planarizing the flowable oxide down to about a level of the top surface of the insulating layer. Further, the method includes, etching through the flowable oxide within the trench and through insulating material at the bottom of the trench down to the underlying device layer to form a via.

Method of forming multi-level coplanar metal/insulator films using dual damascene with sacrificial flowable oxide

Growing community of inventors

Dresden, Germany

Klaus Feldner