Infineon Technologies Ag

Qimonda Ag

Adesto Technology Corporation

Siemens Solar Gmbh

Klaus-Dieter Ufert

Cay-Uwe Pinnow

Josef Willer

Franz Kreupl

Michael Kund

Ralf Symanczyk

Thomas Happ

Wolfgang Raberg

Ulrich Karl Klostermann

Ulrike Gruening-von Schwerin

Bernhard Ruf

Petra Majewski

Dieter Andres

Rainer Bruchhaus

Christian Ruester

Method of fabricating an integrated electronic circuit with programmable resistance cells, which comprises providing a substrate; forming an inert electrode; forming a solid electrolyte on the inert electrode; forming an interlayer on the solid electrolyte, the interlayer comprising an active electrode material and nitrogen; and forming an active electrode on the interlayer, the active electrode comprising the active electrode material.

Method of fabricating an integrated electronic circuit with programmable resistance cells

According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element.

Integrated circuit

A method for producing a solid electrolyte material region for a memory element of a solid electrolyte memory cell. A first material is formed in substantially pure form. A thermal treatment is carried out in the presence of at least one second material, and the chalcogenide material of the solid electrolyte material region thereby being produced.

Method for producing memory having a solid electrolyte material region

An information storage element has a carbon storage material including hexagonally bonded carbon and tetrahedrally bonded carbon. The information is formed by a changeable ratio of hexagonally bonded carbon and tetrahedrally bonded carbon.

Memory element using reversible switching between SP2 and SP3 hybridized carbon

An integrated circuit including a memory element and method for manufacturing the integrated circuit are described. In some embodiments, the memory element includes a switching layer that selectively switches between a low resistance state and a high resistance state, and a positive temperature coefficient layer in thermal contact with the switching layer, the positive temperature coefficient layer having a resistance that increases in response to an increase in temperature.

Memory element with positive temperature coefficient layer

An integrated circuit is described, including a memory element including a first carbon layer rich in a first carbon material and a second carbon layer rich in a second carbon material. The memory element stores information by reversibly forming a conductive channel in the second carbon layer, wherein the conductive channel includes the first carbon material.

Carbon filament memory and fabrication method

An integrated semiconductor memory includes a storage medium () arranged between two electrodes (), which storage medium may be a phase change medium, for example. The storage medium () can be put into a first state or a second state by means of an electric current, as a result of which an item of information can be stored. According to embodiments of the invention, a layer plane (L) is provided in which impurity particles made from a material () are embedded, as a result of which the current density in the storage medium is locally increased and the programming current required for reprogramming is reduced. As a result, the current consumption of memory elements containing a phase change medium is reduced, so that for the first time they can be embodied with minimal feature size, together with other components such as transistors, and integrated into a single semiconductor circuit and no longer have to be arranged in separate subcircuits.

Integrated circuit having a resistive memory

A method for manufacturing an electrolyte material layer with a chalcogenide material incorporated or deposited therein for use in semiconductor memory devices, in particular resistively-switching memory devices or components. The method comprises the steps of producing a semiconductor substrate, depositing a binary chalcogenide layer onto the semiconductor substrate, depositing a sulphur-containing layer onto the binary chalcogenide layer, and creating a ternary chalcogenide layer comprising at least two different chalcogenide compounds ASeS. One component A of the chalcogenide compounds ASeScomprises materials of the IV elements main group, e.g., Ge, Si, or of a transition metal, preferably of the group consisting of Zn, Cd, Hg, or a combination thereof.

Method for manufacturing an integrated circuit including an electrolyte material layer

An integrated circuit including a memory cell and a method of manufacturing the integrated circuit are described. The memory cell includes a buried gate select transistor and a resistive memory element coupled to the buried gate select transistor. The resistive memory element stores information based on a resistivity of the resistive memory element.

Resistive memory element and method of fabrication

A method for manufacturing CBRAM switching elements and CBRAM semiconductor memories with improved switching characteristics so as to remove superfluous, weak, cluster-like, or unbound selenium at the surface of a GeSe layer is solved by the present invention in that, after the generation of an active matrix material or GeSe layer, respectively, a reactive sputter etching process is performed in which the surface layer of the active matrix material or GeSe layer, respectively, is removed at least partially so as to modify the surface structure thereof.

Method for manufacturing a CBRAM semiconductor memory

A nonvolatile memory cell, a memory device and a corresponding production method are disclosed. In one embodiment, a memory material region is in this case provided as memory element between a first electrode device and a second electrode device. The memory material region can be activated by means of at least one species. The memory material region is formed with or from a nanostructure.

Memory cell, memory device and method for the production thereof

A programmable resistive memory cell comprising a lower electrode, a programmable resistance layer, and an upper electrode, wherein a lower mask is arranged between the lower electrode and the programmable resistance layer and an upper mask is arranged between the programmable resistance layer and the upper electrode, and wherein the lower mask and the upper mask comprise current-inhibiting regions.

Programmable resistive memory cell with a programmable resistance layer

A switching element for reversible switching between an electrically insulating OFF state and an electrically conductive ON state, having two electrodes, namely a reactive electrode and an inert electrode, and also a solid electrolyte arranged between the two electrodes, which is characterized by the fact that the electrical conductivity of the solid electrolyte increases as the temperature thereof rises, but essentially no longer increases below a critical decomposition temperature of the solid electrolyte.

Solid electrolyte switching element

Wordline stacks are arranged parallel at a distance from one another on a substrate surface. Bitlines are arranged transversely to the wordline stacks at a distance from one another. Source/drain regions are formed as doped regions in the vicinity of the wordline stacks. A resistive layer is disposed between a plurality of the source/drain regions and the bitlines and formed of a material having a resistance that is switched by an applied voltage. Source lines are arranged parallel to the wordline stacks so that they connect further pluralities of the source/drain regions.

Growing community of inventors

Unterschleissheim, Germany

Klaus-Dieter Ufert