International Business Machines Corporation

Klaus-Dieter Schubert

Derek E Williams

Viresh Paruthi

Wolfgang Roesner

Stephen Gerard Shuma

Benedikt Geukes

Ali S El-Zein

Johannes Koesters

Chung-Lung K Shum

Robert Alan Cargnoni

Michael H Wood

Alvan Wing Ng

Bodo Hoppe

Marshall Dale Tiner

Stephen J Barnfield

Elspeth Anne Huston

Birgit Schubert

Thomas Pfl&uuml;ger

Edward Armayor McQuade

Frank Armbruster

A first plurality of hardware description language (HDL) files describe a hierarchical integrated circuit design utilizing a simplified HDL syntax that omits specification of logical clock connections for at least some entities in the hierarchical integrated circuit design. The hierarchical integrated circuit design as described by the first plurality of HDL files is processed to automatically add logical clock connections for entities in the hierarchical integrated circuit design for which specification of logical clock connections are omitted in the first plurality of HDL files. Based on the processing, a second plurality of HDL files defining the hierarchical integrated circuit design is generated.

Logical clock connection in an integrated circuit design

A processor receives, as input, a first hardware description language (HDL) file defining an entity of a modular circuit design. The first HDL file instantiates, by a storage element declaration in a hardware description language, a storage element within the entity. The first HDL file omits a port map for the storage element. Based on the first HDL file, the processor automatically fully elaborates a port map for the storage element. The processor stores, in data storage, a derived second HDL file defining the entity and including the port map.

Clock mapping in an integrated circuit design

An aspect includes a computer program product for implementing a model of an electrical circuit including a first region and a second region, the first region including simulated logic and a simulated latch circuit. The computer program product includes a tangible storage medium readable by a processing circuit for performing a method. The method includes receiving, as simulated logical inputs to the simulated logic a simulated power supply voltage state of the first region, a simulated data input signal and a simulated clock signal. The method also includes generating, based on determining that the simulated power supply voltage state of the first region corresponds to an inactive state of the first region, a pseudo-random number as an output of the simulated latch circuit, the pseudo-random number generated based on the simulated data input signal and the simulated data output signal from the simulated latch circuit.

Testing two-state logic power island interface

The present invention generally relates to hardware development and design, and in particular it relates to a method for simulating hardware. A meta model () is compiled for integrating a plurality of n different instantiations (A, . . .N) of the same hardware model, and facilities and signals of different instantiations are resolved by instantiation-specific name space specifications in a code switch (). Thus, computing time is saved because by simulating the meta model, the processor resources, for instance, storage spaces, are utilized more efficiently.

Method for parallel simulation on a single microprocessor using meta-models

Disclosed is a hardware design development tool, where in a first step the data flow (,) of the desired hardware design is specified (,) and structured into functions. Then the required control logic (,) is introduced in those functions in order to get a description of the functional behavior of the underlying hardware. Various interconnections or relationships are provided between data flow and control logic, for instance via calls (,) between them. According to the proposed methodological steps, the design is specified (,) by functions depending on variables, wherein the functions contain data flow and control flow information. The functional description is parsed (,) in order to distinguish data flow and control flow information. In particular, at least one local table (,) each entry of which containing the control flow information, and a global table (,) each entry of which containing the data flow information and references to the local table(s), are provided. The development tool allows an automatic generation of a netlist from a high-level functional hardware description. Therefore a slow simulation on the low-level netlist stage is obsolete and the relatively fast simulation of the functional description is sufficient for testing the designed hardware.

Methods and systems for functionally describing a digital hardware design and for converting a functional specification of same into a netlist

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Schoenaich, Germany

Klaus-Dieter Schubert