Other

Infineon Technologies Ag

Klaus Buchner

Klemens Kordik

Bernhard Gstoettenbauer

Thomas Sailer

Christian Unhold

A monitor circuit for monitoring a clock signal is described. In accordance with one example of the disclosure, the monitor circuit includes a pulse generator and a comparator circuit. The pulse generator is configured to generate a sequence of pulses synchronous to the clock signal, wherein each pulse has an edge with a monotonously rising or falling signal level. The comparator circuit receives the sequence of pulses and is configured to detect, for each clock cycle of the clock signal, whether or not the signal level of the sequence of pulses is outside a desired range at a specific time instant within the clock cycle of the clock signal.

Clock monitoring for sequential logic circuits

An interface circuit includes an interface terminal, a voltage detection device, an output driver and an enable logic. The interface terminal is configured to connect to an interface line. The voltage detection device is configured to detect a voltage present at the interface terminal. The output driver is configured to apply an output signal to the interface terminal. The enable logic is configured to generate an enable signal for the output driver based on an evaluation signal output by the voltage detection device, wherein the enable signal affects an enabling of the output driver if the evaluation signal shows that the voltage present at the interface terminal meets a given condition.

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Steyregg, Austria

Klaus Buchner