Asea Brown Boveri Inc.

Asea Brown Boveri Ag

Klas Lilja

Friedhelm Bauer

Thomas Stockmeier

Kenneth Johansson

A power semiconductor component is specified which provides for a significant reduction in the thickness of the semiconductor substrate (1) whilst at the same time optimizing the switching losses. A transparent emitter (6) and a stop layer (7) are arranged to provide a thin semiconductor and optimized switching losses. The means can be used both in semiconductor switches such as IGBT, MCT or GTO and in diodes.

Power semiconductor component with transparent emitter and stop layer

A controlled turn-off power semiconductor device is proposed which is subdivided into unit cells and which comprises five layers in a p-n-p-n-p sequence, namely a p-type emitter layer (9), an n-type base layer (8), a p-type base layer (7), an n-type emitter layer (6) and a p-doped contact region (5) between an anode (a) and a cathode (K). In every unit cell a first MOSFET (M1) which can be driven via a first insulated gate (G1) is provided on the cathode side for switching between the five-layer structure and a conventional thyristor four-layer structure. Further, a breakdown between the contact region (5) and the n-type emitter layer (6) is prevented during turning-off. As a result of the switchable five-layer structure, a current filamentation is effectively avoided during turning-off.

Controlled turn-off power semiconductor device

A turn-off power semiconductor component subdivided into unit cells (EZ), including between an anode (A) and a cathode (K) in a semiconductor substrate (1) five layers in p-n-p-n-p sequence, namely an anode layer (10) an n-type base layer (9), a p-type base layer (8), a turn-off region (6), a cathode region (7) adjoining the turn-off region, and a p-doped short-circuit region (5). On the cathode side in every unit cell (EZ), a first MOSFET (M1) which can be driven via a first insulated gate electrode (G1) is provided for the purpose of switching between the five-layer structure and a conventional thyristor four-layer structure. A second MOSFET (M2) having a second gate electrode (G2) prevents a breakdown between the p-type short-circuit region (5) and the turn-off region (6) during turn-off. p-Type short-circuit region (5), turn-off region (6) and cathode region (7) are introduced in a self-aligning manner into the semiconductor substrate (1) through the windows (F1, F2) between the gate electrodes (G 1 and G2, respectively). Current filamentation during turn-off is effectively avoided by the switchable five-layer structure. The self-aligning production makes possible a component having precise patterning.

Growing community of inventors

Fislisbach, Switzerland

Klas Lilja