Standard Microsystems Corporation

Motorola Corporation

Qualcomm Incorporated

Freescale Semiconductor,inc.

Klaas Wortel

David K Lovelace

Luis Briones

Troy L Stockstad

William Eric Main

Jeffrey C Durec

Danielle L Coffing

Vincent K Jones

James R MacDonald

James M Gardner

Henry Wurzburg

Dennis L Welty

Rainer Gaethke

Thomas Somerville

Trenton B Henry

Karl J Huehne

Guy A Stewart

K Juergen Schoepf

Mike McGinn

Systems and methodologies are described that facilitate calibration techniques for a station in a wireless communication system that can be utilized to provide joint estimates for distortion introduced by in-phase and quadrature (I/Q) imbalance and mixing-product modulated images.

I/Q calibration for walking-IF architectures

A current-mode direct conversion RF receiver is presented. In one set of embodiments the RF receiver comprises a simple transconductor input stage to create a current-mode modulated signal from a voltage-mode modulated signal. A downconversion mixer may be coupled to the transconductor input stage via a low impedance current cascode stage, and may operate to create a set of current-mode quadrature baseband signals from the current-mode modulated signal. The downconversion mixer may be implemented with a transistor-switching network, which may be driven by a phase locked loop (PLL) with quadrature outputs. The set of current-mode quadrature baseband signals may be converted back to the voltage domain by a transimpedance filter, which may perform channel selection for the receiver. The transimpedance filter may additionally include a low frequency zero to remove DC offsets. The receiver may be implemented using CMOS design technologies and operated with minimal self-mixing effects, minimal DC offset in the baseband signal, and utilizing low voltages.

Current-mode direct conversion receiver

A system and method for maintaining communications with a radio frequency (RF) peripheral device such as an RF input device and an RF output device. A computer may search for an RF peripheral device by transmitting a signal request on available channels until a response is received from an RF peripheral device. If the RF channel becomes busy and/or jammed, the RF peripheral device may tune into a predetermined channel while the computer scans for another channel to use. Once the computer finds a better channel, the computer may go to the predetermined channel and broadcast the new channel location to the RF peripheral device. In addition, if an RF signal arrives incomplete or corrupt, the computer may transmit a negative acknowledgement to the RF peripheral device, which may retransmit the previous RF signal.

Communication protocol for personal computer system human interface devices over a low bandwidth, bi-directional radio frequency link

Detecting a radio frequency (RF) environment around a computer and using a power management scheme for an RF user input device being used by the computer system. If the computer system is in a single user environment, a power management scheme may be used to conserve power on the RF user input device. If the computer system is in a multi-user environment, a power management scheme may be used to minimize interference between neighboring computer systems by minimizing the signal strength of the RF signal from the RF user input device and the RF signal from the computer system.

Selective implementation of power management schemes based on detected computer operating environment

A radio transmitter system designed using an FSK modulator with IQ up-mixers and sinewave coded digital-to-analog converters (DACs). The radio transmitter system may include a frequency shift keying (FSK) coding logic circuit coupled to the inputs of an IQ modulation and image reject up-mixer through a respective DAC and a respective low pass filter (LPF) for each the I and the Q channels. The FSK modulation scheme may employ sine and cosine signals for the I and Q channels, respectively, where the sine and cosine waves are directly coded into the DACs. The coded levels required by the DACs may be generated using current sources and may be Gray-coded. The output of the IQ modulation and image reject up-mixer may be connected to a power amplifier, which may be used to transmit the modulated RF signal via a loop antenna.

FSK modulator using IQ up-mixers and sinewave coded DACs

An integrated demodulator tuning circuit () receives differential currents at input terminals () and provides an AFC signal at an output terminal (). The AFC current characteristic has a dead band () in the output current generated when the integrated demodulator tuning circuit () operates under the condition where the difference between the currents supplied at the input terminals (and) is at or below a set threshold value. The set threshold value is determined by the relative sizes of the transistors (andand) that form the current mirrors connected to the input terminals ().

Circuit and method for processing an automatic frequency control signal

An amplifier circuit. In one embodiment, the amplifier includes a first pair of transistors and a second pair of transistors. Each transistor in the amplifier includes a control terminal (e.g. a gate) as well as a first and second terminals. In one embodiment, the transistors are field effect transistors (FETs) and thus the first and second terminals may be either source or drain terminals. First terminals of each of the first pair of transistors may be coupled to a voltage source. The first terminal of each of the second pair of transistors is coupled to the second terminal of one of the first pair of transistors. A current source may be coupled between each of the second terminals and a voltage reference (e.g. ground plane).

Current controlled bridge amplifier

Various embodiments of methods and apparatus for an amplifier with wide output voltage swing are disclosed. The amplifier may include multiple output stages, each associated with a distinct supply voltage. Each output stage may contribute current to the output of the amplifier over a range of amplifier output voltages and these ranges may overlap. Each output stage may contribute current until the amplifier output voltage reaches the supply voltage associated with that output stage. The amplifier output may be as great as the largest supply voltage minus a drop equal to Rdson for an output transistor multiplied by the output current. In a CMOS implementation, this voltage drop may be approximately 0.15V. When the amplifier output voltage is close to the supply voltage associated with an output stage, both that output stage and the output stage associated with the next highest supply voltage may contribute to the amplifier output.

Efficient class-G amplifier with wide output voltage swing

An oscillator circuit. In one embodiment, the oscillator includes a gain circuit, an envelope detector, and an amplitude comparison circuit. The trans-conductance circuit is configured to amplify a periodic signal produced by a crystal. Amplitude peaks of the periodic signal may be detected in the envelope detector, which may determine an average amplitude value based on the detected peaks. The average amplitude value may be compared to a DC voltage value in an amplitude comparison circuit. The DC voltage value may include both a DC average of the periodic signal as well as a predetermined DC offset value. The gain circuit may adjust the level of amplification of the periodic signal based on a feedback signal in order to ensure that the oscillator produces a periodic output signal at a desired level so as to insure oscillation and the minimum use of current to achieve oscillations.

Crystal oscillator with control feedback to maintain oscillation

A low-power phase detector with differential output may comprise a control signal generator. In one embodiment, two cyclic waveforms whose phase relationship is to be measured may be input to a control signal generator. The control signal generator may output a first control signal corresponding to the first cyclic waveform such that the control signal is de-asserted at a specific point with respect to the first cyclic waveform. For example, the control signal may be de-asserted corresponding to the rising edge of the first cyclic waveform. The control signal generator may also output a second control signal corresponding to the second cyclic waveform such that the control signal is asserted at a specific point with respect to the second cyclic waveform. For example, the control signal may be asserted corresponding to the falling edge of the second cyclic waveform.

Phase detector for low power applications

A filter circuit. In one embodiment, the filter circuit includes a continuous time (CT) filter, a switched capacitor (SWC) filter, and an SWC integrator. The CT filter is coupled to receive an input signal from an external source. The CT filter may be a low-pass filter. The SWC filter is coupled to receive an output signal from the CT filter, and provide an output information signal. The SWC filter may also be a low pass filter. A feedback loop may be present between the output of the SWC filter and the input of the CT filter. The SWC integrator samples the output signal from the SWC filter and provides an output signal to the CT filter. The output signal is combined with the input signal to the CT filter. A D.C. offset may be substantially removed from the information signal provided by the output of the SWC filter.

Baseband filter for receivers

A PLL system ( ) includes a clock sequence generator ( ). Clock sequence generator ( ) provides a clock that steps down from a fast frequency through several steps to a frequency of zero. This step-down non-linear digression of frequencies causes a counter ( ) driving a tank circuit of a self-calibrating VCO to achieve lock at an extremely rapid rate. The PFD ( ) generates an analog signal based on the phase and frequency relationship of the reference and feedback clock signals. The analog signal is compared against an upper and lower reference voltage in a threshold detect circuit ( ) and the signals UP and DOWN are supplied to the counter ( ). The counter ( ) provides a count value that controls the resonant frequency generated by the tank circuit. The convergence speed of the PLL system ( ) is accelerated by the effects of the step-down clock provided by the clock sequence generator ( ).

Step-down clock control and method for improving convergence for a digitally controlled self-calibrating VCO

A demodulator circuit ( ) includes an oscillator ( ) and an injection circuit ( ). An Automatic Frequency Control (AFC) signal adjusts the tail current of a current source ( ) provided in the oscillator ( ) and the tail current of a current source ( ) provided in the injection circuit ( ). A phase detector ( ) compares the phase of the signal generated by the oscillator ( ) with the phase of the injected input signal. The phase detector ( ) generates an output signal V having a value of zero when the input signal is in quadrature with the signal generated by the oscillator ( ), but generates a non-zero signal that is used to adjust the AFC signal when the input signal and the signal generated by the oscillator ( ) are not in quadrature.

Demodulator circuit and method of tuning

A mixer (,) has a differential transistor pair (,) receiving first and second reference currents at first and second nodes (,). An RF signal drives the differential transistor pair. A first switching circuit (,) is coupled to the first node and a second switching circuit (,) is coupled to the second node. An LO signal drives the first and second switching circuits. The first and second switching circuit each have first and second outputs that are cross-coupled at output nodes (,) to provide a differential IF output current representative of the sum and difference between the frequency of the RF signal and the frequency of the LO signal.

Circuit and method of signal frequency conversion

A circuit (30) and method for translating a spectrum of a modulated signal. The circuit (30) includes a mixer (33), a summing device (36), and a synthesizer (37). The circuit (30) receives and transmits modulated Radio Frequency (RF) signals. The synthesizer (37) generates a transmitter modulated RF signal (TX.sub.RF) using a modulating signal (TX.sub.MOD). The mixer (33) generates an intermediate frequency signal (IF) by mixing a receiver modulated RF signal (RX.sub.RF) with the transmitter modulated RF signal (TX.sub.RF). The summing device (36) removes modulation of the transmitter modulated RF signal (TX.sub.RF) by combining the intermediate frequency signal (IF) with the modulating signal (TX.sub.MOD).

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Phoenix, AZ, United States of America

Klaas Wortel