Samsung Electronics Co., Ltd.

Seoul National University

Kiyoung Choi

Seungwon Lee

Dongwoo Lee

Namhyung Kim

Sangheon Lee

Soojung Ryu

Hanmin Park

Woong Seo

Sungbum Kang

Junwhan Ahn

Jaehyun Kim

Jinho Lee

Donghyun Lee

Sungjoo Yoo

Gunhee Lee

Deokjin Joo

Jun-whan Ahn

Sung-joo Yoo

Kyungmi Lee

Euntae Choi

Joonsang Yu

Sujeong Jo

Hossein Moradian Sardroudi

Sungju Han

A processor-implemented method of processing neural network data includes: setting first limit data by performing a first operation based on first input data and weight data generated from weights included in a filter; comparing the first limit data with an intermediate result of a second operation performed based on second input data and the weight data; and determining whether to perform a subsequent second operation based on a result of the comparing.

Method and apparatus with data processing

A method of processing an add operation in a processing apparatus includes acquiring sub-operands from input operands each having an n-bit precision, acquiring intermediate addition results by performing add operations of sub-operands in parallel by using adders, bit-shifting each of the intermediate addition results such that the intermediate addition results correspond to original bit positions in the input operands, and outputting a final addition result of the add operations of the input operands based on the bit-shifted intermediate addition results.

Processing apparatus and method of processing add operation therein

A memory controller includes a dirty group detector configured to, in response to receiving a request for writing data to a memory, modify addresses of a cache group related to a physical address of the memory, increase counters corresponding to the modified addresses of the cache group, and detect whether the cache group is in a dirty state based on the counters; and a dirty list manager configured to manage the cache group in the dirty state and a dirty list including dirty bits according to a result of the detecting; wherein the dirty bits indicate whether a cache set included in the cache group is in the dirty state.

Method and device for controlling memory

A method of accelerating a training process of a neural network includes acquiring activations used in the training process and a bit-vector corresponding to the activations, selecting activations requiring an operation from among the acquired activations by using the bit-vector, and performing backward propagation using the selected activations and filters corresponding to the selected activations.

Method of accelerating training process of neural network and neural network device thereof

A processor-implemented data processing method includes encoding a plurality of weights of a filter of a neural network using an inverted two's complement fixed-point format; generating weight data based on values of the encoded weights corresponding to same filter positions of a plurality of filters; and performing an operation on the weight data and input activation data using a bit-serial scheme to control when to perform an activation function with respect to the weight data and input activation data.

Method and apparatus with bit-serial data processing of a neural network

A method of performing a class incremental learning in a neural network apparatus, the method including training an autoencoder using first input embeddings with respect to a first class group, calculating a contribution value of each of parameters of the autoencoder and calculating a representative value with respect to each of at least one first class included in the first class group in the training of the autoencoder, retraining the autoencoder using second input embeddings with respect to a second class group, and updating the contribution value of the each of the parameters and calculating a representative value with respect to each of at least one second class included in the second class group in the retraining the autoencoder.

Apparatus for performing class incremental learning and method of operating the apparatus

A computing apparatus may process an operation. The computing apparatus may output information regarding an aggregation operation and an operand corresponding to a variable stored in a memory, store information regarding an operator and the aggregation operands regarding the aggregation operation, perform a first partial operation with respect to the aggregation operands and store a result value of the first partial operation, and process the aggregation operation based on storing the variable, performing a second partial operation with respect to the result value of the first partial operation stored in the cache and the operand corresponding to the variable, and storing a result value of the second partial operation.

Computing apparatuses and methods of processing operations thereof

Provided is a method and apparatus for processing instructions using a processing-in-memory (PIM). A PIM management apparatus includes: a PIM directory comprising a reader-writer lock regarding a memory address that an instruction accesses; and a locality tracer configured to figure out locality regarding the memory address that the instruction accesses and determine whether or not an object that executes the instruction is a PIM.

Method and apparatus for processing instructions using processing-in-memory

In a method and device to align phases of a first clock signal and a second clock signal, include a phase detector, a delay generator, and a controller. The phase detector is configured to generate a preceding signal and a succeeding signal with respect to the first clock signal to detect a relationship between phases of the first clock signal and the second clock signal. The delay generator is configured to delay the first clock signal when the second clock signal falls behind the succeeding signal with respect to the first clock signal. The controller is configured to determine whether the phases of the first clock signal and the second clock signal are aligned with each other according to the relationship detected by the phase detector.

Method and device to align phases of clock signals

Provided is a multi network and method to transmit packets. The multi network includes a mesh network, a tree network, and a network interface connected to the mesh network and the tree network and configured to transmit, through the mesh network and the tree network, a packet generated by a processing unit, of a processing system having plural processing units, at a starting point to a destination point for another processing unit of the processing system and configured to selectively inject the packet into one of the mesh network and the tree network to transmit the packet to the other processing unit.

Apparatus and method transmitting packets

A method of managing a cache includes storing first data of an upper level cache in a lower level cache, predicting a reuse distance level of second data having a same signature as the first data based on access information about the first data, and storing the second data in one of the lower level cache and a main memory based on the predicted reuse distance level of the second data.

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Seoul, South Korea

Kiyoung Choi