Hitachi, Ltd.

Hitachi Ulsi Engineering Corp.

Hitachi Vlsi Engineering Corp.

Kiyotsugu Ueda

Koichiro Ishibashi

Shoji Hanamura

Kunihiro Komiyaji

Katsuro Sasaki

Hiroshi Toyoshima

Masaaki Kubotera

Takao Oono

Toshiaki Yamanaka

Yoshio Sakai

Naotaka Hashimoto

Toshiaki Masuhara

Osamu Minato

Nobuyuki Moriwaki

Shigeru Honjyo

A semiconductor memory device is provided which is able to supply data at high speed to a microprocessor (MPU) without being affected by the dispersion of power supply voltage, temperature and production process conditions. A semiconductor chip includes an address buffer, a decoder, a word driver, data lines, a sense amplifier, a main amplifier, an output buffer, and a PLL to which an external clock is applied. The PLL generates controls signals .PHI..sub.1 through .PHI..sub.7 with their phases shifted in turn, and supplies them to those internal circuits ranging from the address buffer to the output buffer. The PLL can control the phases of these control signals to be constant without being affected by the variations of temperature and power supply voltage. Thus, the internal circuits are precharged or equalized by the control signals, and then operated by the control signals to amplify data signal in turn. Therefore, the operating cycle time can be shortened as compared with the access time, and the access time can be kept constant.

Semiconductor memory device

In a semiconductor memory device, amplification of data is realized with a high speed without influences of fluctuations at fabrication. Potentials of a common data line pair are set at a reference voltage by current negative feedback of differential amplifiers. In this way signal amplitude in the common data line pair is decreased. A current from a memory cell is transformed into a voltage by transistors in a negative feedback loop. Even if there are fluctuations or an offset voltage in the differential amplifiers, it is possible to decrease the signal amplitude in the common data line pair and to realize a high speed data amplification with low electric power consumption.

Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage sense amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circuit is connected to the complementary inputs of each stage of the multi-stage sense amplifier, an inverse information read operation can be executed at high speed. Initially, the initial stage sense amplifier, the post-stage sense amplifier and the main amplifier are controlled to operate in high amplification gain conditions so as to execute high speed sense amplification and thereafter controlled to operate in such low power consumption conditions that the read-out information output obtained by the high speed sense amplification will not disappear.

Static type semiconductor memory

Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage snese amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circuit is connected to the complementary inputs of each stage of the multi-stage sense amplifier, an inverse information read operation can be executed at high speed. Initially, the initial stage sense amplifier, the post-stage sense amplifier and the main amplifier are controlled to operate in high amplification gain conditions so as to execute high speed sense amplification and thereafter controlled to operate in such low power consumption conditions that the read-out information output obtained by the high speed sense amplification will not disappear.

Static type semiconductor memory with multi-stage sense amplifier

Each of the memory cells in a SRAM includes two driver MOS transistors, two transfer gate MOS transistors and two load resistances. The gate electrode layers of the MOS transistors are formed from a first-level conductive layer provided on the surface of a semiconductor substrate. The source regions of the two driver MOS transistors in each memory cell are connected in common and further connected to a ground potential point through a second-level conductive layer. The two load resistances in each memory cell are formed from a third-level high-resistance material layer. The second-level conductive layer is formed from a low-resistance material layer. Thus the resistance of the sources of the two driver MOS transistors is lowered.

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Hachioji, Japan

Kiyotsugu Ueda