Sharp Kabushiki Kaisha Corporation

Sharp Kabushiki Kiasha

Kiyotoshi Nakagawa

Katsumasa Fujii

Yasuo Torimaru

Tsutomu Ashida

Takeo Fujimoto

Tetuo Biwa

Kenzo Kawano

Katsumi Miyano

A metal oxide semiconductor device is featured by the provision of a covering element for covering a channel region of the semiconductor device there being interposed therebetween an insulating layer. The covering element is connected to at least one electrode selected from the drain electrode, the source electrode and the gate electrode. Therefore, the electrical level of the covering element is fixed.

High voltage MOS transistor

A high voltage MOS field-effect semiconductor device comprising, as formed on a single seimconductor substrate a high voltage first MOS field-effect transistor and a conventional second MOS field-effect transistor operable at a lower voltage than the first transistor. The semiconductor substrate is covered with an aluminum or like conductor layer over the region thereof where the conventional second field-effect transistor is located.

High voltage MOS field effect semiconductor device

A MOS transistor is featured by providing mult-layered covering elements for covering a channel region of the semiconductor device. Each of the covering elements is interposed by an insulating layer. Preferably, the covering layers comprise first and second covering layers neither of which are connected to either of the drain electrode, the source electrode, or the gate electrode. A field plate layer, as a third covering layer, is disposed over the first and second covering layers.

A MOS transistor is featured by the provision of a conductive covering element for covering a drift channel region of the semiconductor device. The covering element is interposed by an insulating layer which is relatively thick. The covering element comprises a floating conductive element, disposed on the insulating layer, and a field plate means, disposed on a second insulating layer.

A metal oxide semiconductor device is featured by the provision of at least two field plate elements interposed by an insulating layer. The field plate elements are connected from a drain electrode and a source electrode. Otherwise, they are isolated from the respective drain electrode, source electrode, and gate electrode. Each of the field plate elements consists of Al, polycrystalline silicon, or the like. An extensive conductive layer is provided which overlaps vertically each of the field plate elements.

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Nara, Japan

Kiyotoshi Nakagawa