Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Kiyoto Ohta

Tomonori Fujimoto

Masanobu Hirose

Yuji Yamasaki

Kenichi Origasa

Masahisa Iida

Toshitaka Uchikoba

Shoji Sakamoto

Hirohito Kikukawa

Masataka Kondo

Kazuhiko Shimakawa

Hiroyuki Sadakata

Yasuhiro Aoyama

Toshikazu Suzuki

Yoshihiko Sumimoto

Emi Hayashi

Hidefumi Ohtsuka

Yoshifumi Fukushima

A temperature sensing circuit activates a sensing signal when sensing that a temperature inside a semiconductor integrated circuit is lower than a predetermined temperature. A heat generation control circuit activates a heat generation control signal when the sensing signal is activated. When the heat generation control signal is activated, a current is generated inside a memory circuit to raise the temperature inside the semiconductor integrated circuit.

Semiconductor integrated circuit

In order to correct an error in input data to thereby obtain write data, in a memory core, an EXOR element performs arithmetic processing based on an output result of an output data latch for latching read data and a result of inputted array input data, and a selector selects a result of the arithmetic processing to prepare write data. Thus, data obtained after performance of the arithmetic processing can be generated in a semiconductor memory by an operation performed immediately after data read. In addition, it is unnecessary to transfer data to an external logic circuit. Therefore, the result of the arithmetic processing can be written to a memory cell block in a subsequent clock.

Semiconductor memory

A semiconductor memory device includes a plurality of memory blocks, a plurality of refresh block counters, a refresh word line counter, and an arbitration circuit. The plurality of refresh block counters generate block addresses of at least two memory blocks to select at least two memory blocks to be refreshed from the plurality of memory blocks. The refresh word line counter generates a common word line address that is common to the at least two memory blocks. The arbitration circuit generates at least one first word line address based on the at least two block addresses and the common word line address and arbitrate so that each word line indicated by the at least one first word line address is refreshed during a period in which a word line indicated by an externally applied second word line address is accessed.

Semiconductor memory device

By simplifying the shape of memory cell diffused mask patterns, the patterns are formed stably and the yield of a semiconductor memory device is improved. Adjacent 2-bit memory cell transistors are formed with one diffused mask pattern, the diffused mask patterns are arranged on a memory cell array, and metal lines are used as source common lines for the memory cells formed at the diffused mask patterns. In this way, that is, by using 2-bit rectangular diffused mask patterns as the memory cell diffused mask patterns and using the metal lines as the source common lines instead of diffused layers, the shape of the memory cell diffused mask patterns is simplified. And furthermore, the continuity of the memory cell diffused mask patterns used as actual memory cells is kept, accuracy in forming the actual memory cell diffused mask patterns is improved, and the yield of the semiconductor memory device is improved.

Semiconductor memory device and method for generating ROM data pattern

A voltage booster power supply circuit using a first voltage VDDand a second voltage VDDM to boost the first voltage VDD, which is higher than the second voltage, to provide a boosted voltage VPP. Thus, a high efficiency of generation of a boosted voltage can be achieved compared with a configuration in which only the second voltage is used to boost the first voltage. A detector circuit detects the boosted voltage VPP to control a voltage booster circuit.

Voltage booster power supply circuit

A semiconductor memory device is provided with a plurality of memory blocks including a plurality of word lines and a plurality of bit line pairs intersecting the individual word lines, a plurality of memory cells provided at each of intersections where the individual word lines intersect the bit line pairs, and a plurality of sense amplifiers respectively provided in correspondence with the bit line pairs. The semiconductor memory device further comprises common data bus line pairs each connected via switch transistors to the corresponding memory blocks, a read/write amplifier for performing a data read/write operation through the common data bus line pairs on the memory blocks, and an SRAM cell electrically connected via switch transistors to each common data bus line pair.

In order to decrease the circuit scale of a power supply circuit and the area occupied by the power supply circuit over a semiconductor substrate, the power supply circuit, which supplies a supply voltage to respective parts of a memory circuit, includes a word driver power supply (first power supply circuit), a sense amplifier power supply (second power supply circuit), a bit line precharge power supply, a cell plate power supply, a substrate bias power supply, and a word line bias power supply. The word driver power supply supplies a word driver with a voltage generated by directly increasing an external supply voltage, whereas the other power supplies (e.g., the sense amplifier power supply) supply a sense amplifier, etc., with a voltage generated by decreasing the external supply voltage.

In a semiconductor device that needs a refresh operation for storing data, data of memory cells selected in response to a row address is read to main amplifiers through bit line pairs, sense amplifiers and data line pairs in a page-mode read operation. Thereafter, while outputting the data held in the main amplifiers to the outside, connecting transistors are turned off so as to disconnect the main amplifiers from the memory cells, and thus, the memory cells can be precharged. Also, in a page-mode write operation, while writing externally supplied input data in the main amplifiers, the memory cells can be precharged.

Semiconductor device having read and write operations corresponding to read and write row control signals

A semiconductor apparatus according to the present invention comprises a current source increasing a current volume in compliance with a rise of a temperature and an oscillation circuit driven by the current of the current source and outputting a clock for refresh control. The semiconductor apparatus, preferably, further comprises a memory device performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof. The semiconductor apparatus, preferably, further comprises a constant voltage source generating a constant voltage using the current source, an oscillation circuit using the current of the current source, and a memory using the constant voltage generated by the constant voltage source as a reference voltage for a power supply circuit and performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof.

Semiconductor apparatus capable of performing refresh control

In a single intersection type (open bit line type) dynamic RAM, sub-arrays are disposed to the left and right sides of a sense amplifier column placed at the center. Each sub-array has a multiplicity of dynamic memory cells. In the subarrays located to the left and right of the sense amplifier column, bit lines in the same row constitute a complementary bit line pair. In each subarray, shielding wiring patterns that are formed parallel to, and in the same wiring layer of, these bit lines are disposed between the bit lines. All of these wiring patterns are set at a fixed potential, such as a power supply potential. Thus, interference noise between adjacent bit lines is effectively reduced.

A row control circuit of a semiconductor memory device includes an oscillator as a clock oscillator for generating an internal clock, a D flipflop as a refresh request signal RFRQ generation circuit for generating a refresh request signal RFRQ synchronously with the internal clock, and a delay circuit, a NAND gate, an AND gate, a D flipflop, a delay circuit, an AND gate and an OR gate as refresh circuits. By using a refresh request signal RFRQ and an active signal ACT, internal refresh is performed internally in a DRAM separately from an external refresh command.

Semiconductor memory device and semiconductor integrated circuit device

Semiconductor memory device in which bit lines connected to dynamic memory cells extend left and right of sense amplifier column

A semiconductor integrated circuit is provided in which a negative voltage generation circuit capable of supplying a memory cell transistor substrate with a stable negative voltage, independently of the fluctuation of a power source voltage or environmental conditions and the process conditions etc., is realized easily, and in which the data holding time of a memory can be secured sufficiently, and the power consumption is reduced. A voltage detection part-B included in the negative voltage generation circuit is provided with a constant voltage generation circuit-B, a measuring voltage generation circuit-B, which receives a constant voltage STDVOUT sent from the constant voltage generation circuit via a voltage supplying circuit-Band a negative voltage VBB sent from a negative voltage generation part and converts it into a measuring voltage REFVby resistors R', R&#x2032;, a first comparator AMPwhich compares the measuring voltage sent from the measuring voltage generation circuit with ground voltage and outputs the result of comparison, and an output buffer circuit-B&#x2032;, which amplifies the compared output from the first comparator and outputs it to the negative voltage generation part.

Semiconductor integrated circuit with negative voltage generation circuit, test method for the same, and recording device and communication equipment having the same

The present invention is a semiconductor memory device provided with bit line pairs to which a plurality of memory cells are attached, a plurality of precharge circuits for precharging the bit line pairs to a first voltage that is different from a mean value between a high level and a low level, a bit line precharge power line for supplying the first voltage for precharging to the precharge circuits, a capacitor, a charging circuit for charging the capacitor, and transfer gate circuits for controlling connection and disconnection of the capacitor and the bit line precharge power line. The transfer gate circuits are controlled so that the capacitor and the precharge power line are connected during precharging of the bit line pairs. Thus, precharging of the bit lines can be performed at high speeds with high precision.

Semiconductor memory device with bit line precharge voltage generating circuit

In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is &ldquo;L&rdquo;, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate. The present invention conducts this test through a scan test, making it possible to automatically create test patterns with high circuit failure detection rate.

Growing community of inventors

Osaka, Japan

Kiyoto Ohta