Ebara Corporation

Nec Corporation

Renesas Electronics Corporation

Kiyoshi Yanagisawa

Osamu Inagawa

Noriaki Matsuno

Toshiya Aramaki

Nobuharu Noji

Norihiko Nomura

Takeshi Kawamura

Noburu Shimizu

Yoshinori Ojima

Kozo Matake

Shigeyoshi Nagata

Toshitsugu Sase

Mitsuru Maeda

Akio Tanaka

Takanori Inada

Yasushi Hisabe

Michiaki Matsuda

Yoshiyuki Maruta

Tokio Fukai

A power line carrier transmission apparatus for transmitting a transmission symbol via a power line, the power line carrier transmission apparatus including an interleave unit interleaving the transmission symbol, a modulation unit for modulating the transmission symbol interleaved by the interleave unit, and a transmission unit repeatedly transmitting the transmission symbol modulated by the modulation unit M times (where M is an integer larger than 1), wherein M symbols (where M denotes the number of the symbols), which are generated by repeatedly transmitting the transmission symbol M times by the transmission unit, are transmitted without guard intervals being added therebetween.

Power line carrier transmission apparatus and communication system

A semiconductor device contains a narrow band noise detector section to detect narrow band noise in an input signal that is input by way of a power line. The semiconductor device further includes a reference signal generator section to generate a second reference signal whose amplitude value which corresponds to the narrow band noise frequency of a pre-established first reference signal is reduced, and a correlation calculation section to calculate the correlation value between the input signal and the second reference signal utilized in the frame synchronization processing of the input signal.

Semiconductor device and receiver

A power line carrier transmission apparatus according to an aspect of the present invention is a power line carrier transmission apparatus that transmits a transmission symbol via a transmission path. The transmission apparatus includes a frequency/time interleave unit that interleaves the transmission symbol, an OFDM modulation unit that OFDM-modulates the interleaved transmission symbol, a time-domain repeated transmission unit that repeatedly transmits the transmission symbol, which is modulated by the OFDM modulation unit, M times (M is an integer larger than 1) in a time domain.

A receiving device according to the present invention includes: a receiver for receiving an OFDM symbol that is modulated by phase shift keying; an FFT processor for applying an FFT process to the received OFDM symbol to obtain a subcarrier signal; a demapping unit for demapping the subcarrier signal to generate a bit string; a norm calculator for calculating the norm of the subcarrier; a weighting factor generator for generating a weighting factor by taking the statistics of the calculated norm; and a weighting unit for obtaining a soft decision value by weighting the bit string after demapping, based on the particular weighting factor. Thus, the receiving device can obtain a soft decision value to achieve good decoding performance with a small number of known signals and processes.

Receiving device, signal processing device, and signal processing method

A signal processing circuit for compensating for an I/Q amplitude mismatch in which the amplitudes of I- and Q-components of output signals of a quadrature modulator are unequal to or for compensating for an I/Q phase mismatch in which the phase difference between the I- and the Q-components of output signals of the quadrature modulator deviates from 90 degrees. The signal processing circuit comprises an I/Q mismatch compensating part that corrects the amplitude or phase of an input signal based on the compensation amount for compensating for an I/Q amplitude mismatch or an I/Q phase mismatch and that inputs the corrected signal into a quadrature modulator; a test signal generating part that sequentially generates and inputs two sets of combined I- and Q-components of a test signal, which is an AC signal, to the I/Q mismatch compensating part; a detector that determines an amplitude of the envelope of an output signal of the quadrature modulator; a filter that passes those ones of output signals of the detector which have frequencies equal to or lower than a cutoff frequency; and a control part that derives an amplitude or phase compensation amount of the I/Q mismatch compensating part such that the output values of the filter at the time of generating the two respective sets of test signals are equal to each other, the control part then inputting the derived amplitude or phase compensation amount into the I/Q mismatch compensating part.

Signal processing circuit and signal processing method

A signal processing circuit, a signal processing method and a recording medium suppressing occurrence of unnecessary waves are provided. A timing generation means which generates timing to select a signal of a predetermined local frequency in a set time period and not to select any signal of all local frequencies in a different set time period, and a plurality of switches which switch over a signal of the local frequency from each multiband generator to the transmission mixer by an instruction from the timing generation means are included.

Signal processing circuit, signal processing method and recording medium

An apparatus includes a test signal generation unit supplying test signals to an orthogonal modulator and a control unit that based on a result of decision by comparison and decision of detection results of a detector detecting envelopes of modulated signals output from the orthogonal modulator responsive to the test signals, derives adjustment values and a compensation value. An estimation means estimates a DC offset and an IQ mismatch of the orthogonal modulator, based on the derived compensation value. The test signals includes a first set including a first test signal (I, Q) and a second test signal (I, Q) having a predetermined relationship with the first test signal, and a second set of which in-phase and quadrature components have predetermined relationships respectively with in-phase and quadrature components of the first set.

Signal processing apparatus and signal processing method

Test signal generator () generates test signals represented, by four points, which comprise two sets of two points positioned in point symmetry with respect to the origin of an I/Q orthogonal coordinate system. Envelope detector () detects the amplitude of an envelope of the output signal from an orthogonal modulator when the test signals represented by four points are generated, and outputs a signal proportional to the square of the amplitude. Comparing unit () calculates an average value of output signals from envelope detector ( ) when the test signals represented by the two points of each set are generated. Controller () adjusts the amplitudes and/or phases of the test signals so that the average values produced when the test signals represented by the two sets of the two points are generated are equal to each other, and calculates an I/Q mismatch quantity based on the adjusted results.

Signal processing circuit

A test signal is generated and supplied to a signal processing circuit for making frequency conversion. A signal outputted from the signal processing circuit is detected to generate a detected signal including a detected positive signal corresponding to the positive signal of the test signal and a detected negative signal corresponding to the negative signal. And the level of the detected positive signal and the level of the detected negative signal are compared to output the comparison result indicating which level is higher. Further, an offset correction signal for making a level difference between the detected positive signal and the detected negative signal within a preset permissible range is generated, based on the comparison result, and offset correction of the test signal or modulated signal supplied from the outside is made in accordance with the offset correction signal.

Signal processing device and method

A signal generator generates a test signal including a positive signal and a negative signal which have the same amplitude. The signal generator corrects a DC level of the test signal based on a DC offset correcting signal supplied thereto, and supplies the corrected test signal to a frequency converter. An amplitude detector detects the amplitudes of the positive and negative signals of the test signal processed by the frequency converter. A level compressor converts in level the amplitudes of the positive and negative signals which are detected by the amplitude detector, with a gain variable depending on an input level thereto. A comparator compares the amplitudes of the positive and negative signals which are converted in level by the level compressor, with each other. An offset adjuster supplies the DC offset correcting signal depending on a compared result from the comparator to the signal generator.

DC offset correcting device and DC offset correcting method

A continuous processing trap apparatus is capable of increasing the trapping efficiency while maintaining conductance required by a vacuum chamber. The trap apparatus includes an exhaust passage for evacuating a hermetically sealed chamber by a vacuum pump, a hermetically sealed trapping and regenerating casing extending across the exhaust passage and a regenerating passage adjacent to the exhaust passage, and a trap unit movably housed in the trapping and regenerating casing for selective movement between a trapping position connected to the exhaust passage and a regenerating position connected to the regenerating passage. The trap apparatus further includes valve bodies disposed one on each side of the trap unit and supporting seals on outer circumferential surfaces thereof for sealing the exhaust passage and the regenerating passage from each other, and a monitoring mechanism for monitoring whether the seals are functioning normally.

Trap apparatus

A vacuum pump has a casing having an inlet port and an outlet port, and a pair of confronting pump rotors which are provided inside the casing and synchronously rotatable for drawing in a gas from the inlet port and discharging the gas from the outlet port. A motor for rotating the confronting pump rotors is a permanent magnet motor having a stator and a motor rotor. The motor rotor has an iron core and permanent magnets disposed within the iron core.

Growing community of inventors

Kanagawa, Japan

Kiyoshi Yanagisawa