Hitachi, Ltd.

Kiyoshi Tsukuda

Atsuo Watanabe

Takahide Ikeda

Tatsuya Kamei

Mitsuru Hirao

Touji Mukai

Shigeru Kawamata

An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

Bimos semiconductor integrated circuit device including high speed

Semiconductor integrated circuit device and a method for manufacturing

An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from a surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

Lateral type semiconductor devices are provided which can withstand a high applied reverse voltage and can be effectively employed in semiconductor integrated circuits with an enhanced integration density. These lateral type semiconductor devices include therein an island region formed in a semiconductor supporting region and a diffusion region formed in the island region. The radius of curvature at the pn junction surface of the diffusion region is selected to be at least 1.5 times larger than the depth of the diffusion region. The diffusion region includes electrode mounting portions of large area and the remaining portions having the form of a fine line.

Lateral type semiconductor devices with enlarged, large radii collector

In a semiconductor switch for use in a telephone exchange, interference between separate switching units located on a single chip is frequently a problem. To overcome this, a semiconductor switch is provided with a plurality of islands of silicon monocrystal disposed in a supporting body of silicon polycrystal through a dielectric film having a plurality of switching circuit islands, at least one driving circuit island, and a plurality of protective circuit islands, wherein a region to reduce parasitic capacitance is formed between said switching circuit islands by arranging the switching circuit islands to be isolated from one another through said region.

Growing community of inventors

Hitachi, Japan

Kiyoshi Tsukuda