International Business Machines Corporation

Kiyoshi Takemura

Nobuyoshi Tanaka

Tadayuki Okada

Makoto Ogawa

Masaki Oie

Stephen P Thompson

Akihiro Ogura

Kiyoshi Nishino

Nishino Kiyoshi

Joseph D Harwood

Data is compressed using content addressable memory without disruption despite error using a plurality of content addressable memories to detect sequentially repeating data elements of the data. Compression information is generated for each sequence of repeating data elements that repeat for at least a compression threshold without any one of the plurality of content addressable memories generating an indication of an error for a matching content addressable memory entry. Individual data elements are output for each of the data elements that do not repeat for the compression threshold. Compression information is generated for each sequence of repeating data elements that repeat for at least the compression threshold and then generating a currently searched data element that matches the repeating data elements when any one of the plurality of content addressable memories generates an indication of an error for a content addressable memory entry that matches the currently searched data element.

Parity error recovery method for string search CAM

A method for decoding encoded data includes receiving data encoded by replacing each of a plurality of characters with bit strings. The method also includes recording, on the basis of definition information, at least one of the characters as corresponding to each of the bit lengths, and generating decode information based on the number of characters, wherein the decode information includes bit string information for sorting the bit strings in a bit length order that is a predetermined order associated with bit lengths. The method also includes, in response to receiving a particular bit length, generating character information in which the characters are sorted in the bit length order by inserting a character corresponding to the particular bit length into a position corresponding to the particular bit length in an array in which at least one of the bit lengths.

Decoding encoded data

An apparatus and method are provided for selecting a specific position from a plurality of positions in a memory to which data elements are cyclically written. A specific data element is stored in the plurality of positions. The apparatus comprises a determination unit for determining whether the plurality of positions include any position in a specific area of the memory to which data elements are written in a current cycle. The apparatus further comprises a selection unit for selecting at least one position in the specific area out of the plurality of positions as the specific position if the determination unit determines that the plurality of positions include any position in the specific area, and for selecting at least one position out of the plurality of positions as the specific position if the determination unit determines that the plurality of positions do not include any position in the specific area.

Selecting a position where data is stored

Data encoded by replacing each of a plurality of characters with bit strings is received. On the basis of definition information, at least one of the characters is recorded as corresponding to each of the bit lengths, and decode information is generated based on the number of characters, wherein the decode information includes bit string information for sorting the bit strings in a bit length order that is a predetermined order associated with bit lengths. In response to receiving a particular bit length, character information in which the characters are sorted in the bit length order is generated by inserting a character corresponding to the particular bit length into a position corresponding to the particular bit length in an array in which at least one of the bit lengths.

Various embodiments are provided to reduce a processing time taken when plural bit lengths each assigned to plural strings are converted into plural codes. In one exemplary embodiment, in response to input of the plurality of bit lengths, a number of strings assigned each of the bit lengths, a bit length assigned to each of the strings, and a sequence number of each string in a group of strings assigned each of the bit lengths are recorded. A plurality of base codes are generated on the basis of the numbers of the strings recorded by the recording unit, the base codes each being a code used as a base for codes having the same one of the bit lengths. A plurality of codes is generated by performing in parallel a plurality of processes respectively for the plurality of strings.

Conversion of bit lengths into codes

A system for horizontal expansion of low resolution display modes onto high resolution displays including flat panels at a variable scaling factor is disclosed. The system may be combined with known methods for vertical expansion to allow low resolution display modes to be expanded onto any high resolution display. Two different methods are provided, one for graphics modes and one for text modes, to attain better screen image quality. In the first method, a first pixel data sequence to be expanded is first oversampled at a multiple of the frequency thereof to produce an intermediate oversampled data sequence. The oversampled data sequence is linearly decimated by a factor of less than unity to produce a replicated second data sequence longer than the first, which is then displayed. In the second method, the intermediate oversampled data sequence is filtered to provide an interpolated oversampled data sequence, which is then decimated instead of the intermediate oversampled data sequence, to further improve the screen image quality. No particular mechanism for the graphics controller or display logic is required, eliminating complicated image processing and enabling the size, complexity and cost of the video subsystem of a computer to be reduced.

Growing community of inventors

Yamato, Japan

Kiyoshi Takemura