Matsushita Electric Industrial Co., Ltd.

Kiyoshi Okamoto

Masaki Toyokura

Toshiyuki Araki

Yoshifumi Matsumoto

Hisashi Kodama

Kunitoshi Aono

Akihiko Ohtani

Takuya Jinbo

In an IDCT circuit, a first RAC and a second RAC each have a ROM for sequentially generating a plurality of partial products and an accumulator for performing a digit-adjustment accumulation of the generated partial products while truncating the LSB of an intermediate accumulation result for every cycle. The first RAC further has a carry bit generator for holding a carry bit of one cycle before and for generating a carry bit of a current cycle by performing a majority arithmetic operation of the LSB of an intermediate accumulation result of the first RAC, the LSB of an intermediate accumulation result of the second RAC and the one-cycle-before carry bit. The second RAC further has a borrow bit generator for holding a borrow bit of one cycle before and for generating a borrow bit of a current cycle by performing a majority arithmetic operation of the LSB of an intermediate accumulation result of the first RAC, an inverted bit of the LSB of an intermediate accumulation result of the second RAC and the one-cycle-before borrow bit. A final accumulation result of the first RAC, a final accumulation result of the second RAC, a final carry bit and a final borrow bit are used in butterfly arithmetic operations.

Product-summing arithmetic circuit

Stored in each of four coefficient memories are eight elements of each row of a matrix in 4 rows and 8 columns, which matrix consists of absolute values of elements of upper four rows out of an inverse discrete cosine matrix in 8 rows and 8 columns to be subjected to an 8-point IDCT processing. An input element y.sub.ij is supplied in parallel to four multipliers. Each of the four multipliers executes multiplication of an output of the corresponding coefficient memory out of the four coefficient memories, by the input element y.sub.ij. Eight accumulators are disposed for executing, in parallel, accumulation for obtaining eight inner products using results of the four multipliers while restoring signs of the coefficients of the orthogonal transform matrix. An 8-input selector is disposed for successively selecting results of the eight accumulators to supply an inner product w.sub.ij corresponding to the input element y.sub.ij.

Orthogonal transform processor

The output of a butterfly unit is entered into a product-sum unit in a forward DCT and the output of the product-sum unit is entered into the butterfly unit in an inverse DCT. The product-sum unit employs, as a bit-string distribution circuit, a register circuit having eight bit shift registers each having a 16-bit parallel input and a 2-bit shift output and the bit shift registers are different in bit width from one another. Data are entered into the bit shift registers with the largest bit-width bit shift register first, such that the respective bit shift registers are shifted rightward by 2 bits per cycle. Four shift registers are disposed between the bit-string distribution circuit and a RAG circuit such that, when bit strings are entered, as delayed cycle by cycle, into eight RAGs of the RAC circuit, the final accumulation results are successively provided from the RACs in a proper order. This reduces the bi-directional DCT processor in circuit arrangement.

In a program control type processor for executing plural instructions including a vector pipeline instruction including a data processor for executing a pipeline operation, there is provided a program controller including a program memory, a program counter and a decoder, and is further provided an address generator and a data memory. When the vector pipeline instruction is read out from the program memory and is decoded by the decoder, the program controller stops the program counter and outputs a start signal, and thereafter, controls an operation of the data processor according to the contents of the vector pipeline instruction. The data processor executes the pipeline operation for the data outputted from the data memory by being controlled by the program controller, and the program controller detects completion of the pipeline operation performed in response to the vector pipeline instruction a predetermined number of cycles after receiving the end signal, and thereafter, sequentially executes instructions following the vector pipeline instruction.

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Osaka, Japan

Kiyoshi Okamoto