Rohm Co., Ltd.

Kiyoshi Nishimura

Takaaki Fuchikami

Hiromi Uenoyama

Hideki Hayashi

Jun Muramoto

A data processing system including first and second data processing devices communicating in a non-contact manner. The first data processing device divides the data into a plurality of data groups and sequentially transmits the data groups to the second data processing device. The second data processing device receives the input data and power from the first data processing unit and processes the input data. A detection control device of the second data processor detects whether the processing of the present data group is successful. If the processing of the present data group is successful, the second data processing device stores the processing result for the present data group in a memory device and transmits a signal to the first data processing device indicating that the processing is successful. The first data processing device then transmits the next data group and the second data processing device continues to process the next data group. If the processing of the present data group is unsuccessful, the second data processing device outputs from the memory the stored processing results for the immediately previous data group, and transmits a signal to the first data processing device indicating that the processing is unsuccessful. The first data processing device then re-transmits the present data group and the second data processing device re-processes the present data group. Whether the processing of the present data group is successful is detected by detecting whether a predetermined electric power is received during a time period in which the present data group is processed.

Data processing system, data processor and data processing method

It is an object of the present invention to provide a simulation apparatus capable of easily evaluating dynamic characteristics of a circuit including a ferroelectric device quantitatively. Means,and,calculate dynamic capacitance of a without-polarization reversal term, Cp, and a with-polarization reversal term, Cr, respectively, by differentiating the without-polarization reversal term fQp and the with-polarization reversal term fQr, respectively, representing simple saturation functions with the voltages applied to the ferroelectric part. Means,calculates dynamic capacitance Cd of the ferroelectric part by composing both the dynamic capacitance Cp and the dynamic capacitance Cr. Means,determines dynamic time constants &tgr; of the circuit including the ferroelectric part in accordance with the dynamic capacitance Cd. Means,determines both transient charge response q(t) and transient current response i(t) and the like in accordance with the time constants &tgr;. The transient responses can be simulated by using the without-polarization reversal term fQp and the with-polarization reversal term fQr both representing simple saturation functions.

Apparatus for simulating electrical characteristics of a circuit including a ferroelectric device and a method for simulating electrical characteristics of a circuit including a ferroelectric device

A control drive circuit or the like is provided that is capable of producing a drive output of a higher voltage than a drive power source voltage. A differential amplifier,that constitutes a differential amplifying section,generates a current Ia on the basis of a current I,obtained with a constant current generating section,and signal waveforms Vina and Vinb inputted from a signal source S. Currents I,and I,are generated with a pre-drive section,The current I,corresponds to part of the current Ia that is greater than 1/2&middot;I,and smaller than 3/4&middot;I,The current I,corresponds to part of the current Ia that is greater than 3/4&middot;I,In other words, part of the current Ia that is greater than 1/2&middot;I,is divided at the threshold value of 3/4&middot;I,to obtain the currents I,and I,Different coils are driven on the basis of the currents I,and I,A drive output of a higher voltage than a drive power source voltage is obtained by synthesizing the outputs produced with the coils.

Control drive circuit and control drive method

An object of the present invention is to provide a ferroelectric storage device which has long life in use. A switch-signal generating portion,automatically generates switch signals in predetermined timing. A reversal-of-polarity controlling portion,changes, on the switch signal, the polarity states of ferroelectric storage cells composing an information storage portion,. After that the reversal-of-polarity controlling portion,further performs a certain number of write operations or read-out operations on said ferroelectric storage cell so as to further move the polarity state in the direction of the changed polarity. A gate controlling portion,gives a control-of-input-gate signal and a control-of-output-gate signal to an input gate portion,and an output gate portion,thereby changing states of their operations. Therefore, the polarity state can be changed if required with the same data being stored in the ferroelectric storage cell. That prevent the ferroelectric storage cell from getting the bad electric property (imprint effect).

Ferroelectric storage device

It is an object to provide signal storing circuits and related devices capable of storing resulting data even when the power supply thereto is suspended, and to provide the signal storing circuit which consumes less power. A logic processing circuit,comprises a combined logic block CB and a latching block LT. The latching block LT includes a line,for passing the resulting data OUT outputted by the logic block CB. A circular signal path (feedback loop) including a line,and another line,overlaps a part of the line,. An inverter circuit INV,made of a ferroelectric transistor is provided to the line,. In this way, the resulting data OUT existing on the line,can be stored in ferroelectrical manner and the data right before the shut-off of the power supply can be reproduced on the line,with the recovery of the power supply. In order to suppress the power consumption, a power control portion,switching the power supplied to the latching block LT is provided to the processing circuit

Signal storing circuit semiconductor device, gate array and IC-card

An object of the present invention is to duplicate functions of a first device into a second device so as to have the same functions as the first device. CPU 23 supplies a predetermined input data to both the second device 19 and the first device 17. A plurality of logic data for generating output data correspond to specific input data are stored in the hard disk 26 as candidates. The CPU 23 selects a candidate which makes both the output data generated by the second device 19 and the first device 17 identical with each other for all the supplied input data within the candidates. The CPU 23 outputs a rewrite command to the second device 19 so as to execute logic data of the candidate thus selected. The output data of the second device 19 identical with the output data generated by the first device 17 can be obtained for all the supplied input data.

Device for duplicating functions and a method for duplicating functions

It is an object of the present invention to provide a ferroelectric memory device including a load capacitor corresponding to an actual read-out time period appropriately and capable of reading out stored data in a high-speed as well as saving electric power consumption. An applying duration 't' (=2.5n seconds) which generates the maximum value of the differential voltage .DELTA.V of approximately 0.87V is selected when a voltage value corresponding the minimum detectable value of the sense amplifier AMP1 is 0.8V. Also, capacitance C of the load capacitor Cb is determined at the capacitance (.apprxeq.1.25 pF) which maximize the differential voltage .DELTA.V when the applying duration 't' is 2.5n seconds. Another applying duration 'tp' (not shown) of read-out voltage Vp is set as 2.5n seconds the same as the applying duration of the voltage Vd for determining characteristics of a capacitor. A duration required for rewrite operation can be shorten when the applying duration 'tp' of read-out voltage Vp is set shorter. In this way, a duration required from read-out operation to rewrite operation can be shorten as well as saving electric power consumption.

Ferroelectric memory device and a method for manufacturing thereof

A switch SW 11 comprises a ferroelectric memory 26 and an AND gate 28. A data input line L11 and an output terminal of the ferroelectric memory 26 are connected to an input terminal of the AND gate 28. Also, output terminal of the AND gate 28 is connected to an AND input line L21. In order to write the switching data which switches the state of the switch SW11 either in open state or closed state into the ferroelectric capacitor 26, ferroelectric capacitors C11 and C12 are polarized in opposite directions with each other. The polarization is carried out in short period, and the polarization state can be maintained even when the power is turned off. So that, the switching data can be written repeatedly by changing direction of the voltage applied to the ferroelectric capacitors C11 and C12.

Programmable functional device having ferroelectric material

It is an object of the present invention to provide a data storing device capable of responding in high speed without providing a power supply just for maintaining the stored data. A memory cell MC11 is made so as to replace only a memory transistor MT1 out of a pair of memory transistors MT1 and MT2 used for the prior art SRAM with a transistor with 'MFMIS structure' having a ferroelectric layer 32. The ferroelectric layer 32 keep storing a polarization state in response to ON state stored in the memory transistor MT1 even when a power supply of the device is turned off. The memory transistor MT1 is turned into ON state in accordance with the polarization state stored in the ferroelectric layer 32 when the power supply is turned on again. In response to the change in state at the memory transistor MT1, the memory transistor MT2 is turned into OFF state. That is, the memory cell MC11 is defined as a ferroelectric memory. In addition, the reversal of the polarity in the ferroelectric layer 32 is carried out in high-speed.

High-speed responding data storing device for maintaining stored data

An object of the present invention is to provide a semiconductor device having a ferroelectric capacitor wherein the ferroelectric capacitor is difficult to get bad electric property. In a capacitor unit CbU for load, a bridge circuit is made including a ferroelectric capacitor Cb for load, transistors Q1, Q2, Q3 and Q4. The both ends of the bridge circuit is connected with a bit line /BL1 and the ground G, respectively. A line SWS is connected with the gates of both transistors Q1 and Q3 and further is connected with the gate of both transistors Q2 and Q4 via an inverter 104. A switch-signal generating circuit 102 shifts the level of switch signal for the line SWS whenever the number of leading edges of the line GCP reaches a predetermined number. According the shifted switch signal, the direction of the capacitor Cb for load in its bridge circuit is changed. That can prevent the capacitor Cb for load from getting a bad electric property.

Semiconductor device with a ferroelectric capacitor

A semiconductor memory device with a plurality of memory cells each having a ferroelectric material for storing a data item by its residual polarization is made usable selectably both as a RAM and as a ROM by controlling the so-called 'imprint condition' of the ferroelectric material. When some of the memory cells are going to be used to a ROM or when the memory cells in an imprint condition are going to be used a RAM, heat and/or voltage pulses with an appropriate polarity are applied to the data-storing ferroelectric material to change its hysteresis characteristics.

Semiconductor memory device and method of controlling imprint condition

It is an object of the present invention to provide a ferroelectric memory device having a high integration and capable of maintaining nonvolatility. A threshold voltage V.sub.th of a ferroelectric memory element is set at value slightly higher than a voltage -V.sub.1. A voltage 0V is applied as a gate voltage V.sub.G when the stored data is read out. A voltage V.sub.1 is generated at a MOS capacitor C.sub.MOS if the data 'High' is stored and the voltage -V.sub.1 is generated at the MOS capacitor C.sub.MOS if the data 'Low' is stored. The stored data is read out by detecting a drain current during generation of the voltages. Also, a voltage 0V is applied as the gate voltage V.sub.G when stand-by operation is carried out. In this way, variation of the gate voltage V.sub.G caused by switching ON and OFF of a power source can be prevented. So that, nonvolatility of the ferroelectric memory device can be maintained as a result of preventing spontaneous polarization of a ferroelectric capacitor C.sub.ferro. Further, it is not necessary to provide a circuit for generating a voltage for using read out the data to the ferroelectric memory device. So that, integration of the ferroelectric memory device can be increased.

Ferroelectric memory device, a method for read out stored data and a

A portable information device includes a portable main part having a clocking function, a source part which is detachably attachable to the main part and contains secondary batteries serving as a power source for the main part, and a charger which is separate from the main part and serves to charge the source part. The charger includes a clock part for setting time, and the information device is adapted to cause time data from the clock part to be transmitted to the source part when the source part is charged by the charger and, when the source part is attached to the main part, to transmit time data updated by the source part to the main part and to thereafter cause the main part to continue updating the time data.

Portable information device and charger therefor

In a data security system, after completion of writing into a P-ROM, a switching circuit is open to thereby disconnect the connection between an internal bus and an external bus. In this state, it is impossible to read the contents out of the P-ROM. To read the contents, a protection releasing terminal is brought to 'H'. This causes a switching circuit to conduct to make possible read-out. The 'H' signal is simultaneously supplied to an erasion signal generating circuit to erase a part selected by an erasion selecting switch. Secrecy is substantially maintained because a program in the P-ROM is not entirely read. The remainder except the erased portion can undergo checking for correctness of writing.

Data security device and method thereof

A semiconductor memory device has a plurality of memory cells, each having a ferroelectric memory capacitor, arranged in a matrix formation in rows and columns. A read-out device is associated with each row for reading out data stored in a selected one of the memory cells in the row based on voltages generated by the ferroelectric capacitor belonging to that selected memory cell and a plurality of divided ferroelectric capacitors which are distributed in the direction of the rows such that piezoelectric effects on the ferroelectric capacitors will be diminished.

Growing community of inventors

Kyoto, Japan

Kiyoshi Nishimura