Fujitsu Corporation

Kiyoshi Miyasaka

Jun-ichi Mogi

Mitsuo Higuchi

Junji Ogawa

Fumio Baba

Seiji Enomoto

Kazuya Kobayashi

Yoshihiro Takemae

Tomio Nakano

Shigeki Nozaki

Junji Sakurai

Takeo Tatematsu

Katsuhiko Kabashima

Hidehiko Akasaki

Tsutomu Mezawa

Takashi Yabu

Junichi Mogi

A semiconductor memory device enables multi-direction data access at a high speed with a simple circuit construction. The semiconductor memory device includes a plurality of word lines, a plurality of bit lines and a plurality of memory cells connected to the bit lines and word lines. A row decoder, connected to the word lines, selects one of the word lines in response to a row address signal. A selection circuit includes a plurality of column decoders and a direction decoder. Each column decoder receives a portion of a column address signal and the direction decoder selects one of three directions in response to a direction address signal. Each column decoder is selectively enabled based upon the direction address signal. Output circuitry outputs data read out from bit lines selected by the enabled column decoders. Thus, three-dimensional bit map data can be stored in two dimensions.

Semiconductor memory device capable of multidirection data access

A modular semiconductor device for use as a memory or used in logic circuit electronic equipment, includes a plurality of IC chips mounted on one or both sides of a printed circuit substrate. The IC chips are grouped into at least two groups which are selectively operated. The IC chips in one group are arranged alternately with the IC chips in the order group to provide a substantially uniform temperature distribution, over the substrate, of heat build-up in the substrate due to activation of the IC chips.

Modular semiconductor device

A semiconductor integrated device with a high tolerance against abnormally high input voltages comprises a first MIS transistor at the input stage and a second MIS transistor of the internal elements of the device. The source of the first MIS transistor is connected to an input electrode. The drain of the first MIS transistor is connected to the gate of the second MIS transistor. The source region of the first MIS transistor comprises phosphoric atoms. The other diffusion regions comprise arsenic atoms. Therefore, the depth of the source region of the first MIS transistor is greater than the other diffusion region. In addition, the source region of the first MIS transistor has a considerable gradient with regard to the concentration of the phosphoric atoms. As a result, the depletion layer between the source region of the first MIS transistor and the semiconductor substrate is broader than in the other region. Consequently, a high tolerance against abnormal high input voltages is obtained.

Semiconductor integrated circuit device with a high tolerance against

A semiconductor device comprising memory circuits coated with a resinous film for shielding these circuits from the radioactive rays formed in substrate material. The resinous film is divided into a plurality of portions which are separated from one another and further coats at least memory cells and sense amplifiers. In one of the embodiments a part of the resinous film is removed at the portion of the chip other than said memory cells and sense amplifiers.

Semiconductor device

The present invention discloses a memory cell layout of a dynamic RAM of a folded bit line type MOS FET wherein the bit line pairs are extended in parallel away from the sense amplifiers. The present invention includes a particular bit line pair and at least one bit line of an adjacent bit line pairs positioned between the particular bit line pair and makes the capacitor regions corresponding to the mutually adjacent bit lines interleave and thereby improves the area efficiency of the capacitor region.

DRAM with interleaved folded bit lines

A semiconductor circuit consisting of a dynamic-type circuit and a bias-voltage generating circuit. The bias-voltage generating circuit is comprised of a first bias-voltage generator and a second bias-voltage generator. The first generator absorbs a variable substrate current, the magnitude of which is proportional to the operating frequency of the dynamic-type circuit, while the second generator absorbs a substrate current, the magnitude of which is not proportional to the operating frequency of the dynamic-type circuit. Alternately, both portions of the substrate current may be absorbed via the same circuitry.

Semiconductor substrate bias circuit

A semiconductor memory device includes in its chip a decoder circuit which receives external selection signals for selecting a memory chip. The decoder circuit performs the selection of the memory chip in accordance with a logic corresponding to the combination of the external selection signals. The selection logic can be changed by the user of the semiconductor device.

Semiconductor memory device with decoder for chip selection/write in

A semiconductor memory device, comprising N memory cell arrays each of which includes a plurality of memory cells, is arranged to enable the use of said semiconductor memory device in the form of both one-bit-per-word N-bits-per-word. Two separate sets of output gates are provided, together with an additional input line for selecting between the two sets of gates. One set of gates is connected to provide one-bit output, and the other set of gates is connected to provide N-bit output.

Semiconductor memory device

An address buffer circuit is used in a memory device, for example in an EPROM device, and enables high speed testing of the memory device. The address buffer circuit can output '1' or '0' from both a positive output terminal and a negative output terminal when an input word address signal having a signal level different from the usual signal level is applied to an input of the address buffer circuit, so that a plurality of word lines can be selected at a time.

Address buffer circuit

A one transistor, one capacitance type dynamic MOS.RAM is provided with a buried storage capacitor and a planar transfer electrode. The MOS.RAM is, therefore, characterized by a small size of the memory cells and a simple production process. One process feature of the present invention is that a quick diffusion through polycrystalline silicon is employed for forming a vertical connection between the buried storage capacitor and the source or drain of the MOS transistor.

MOS Random access memory with buried storage capacitor

A semiconductor device for use in a bootstrap circuit comprising: first and second MIS field effect transistors connected in series between a power supply line and ground; third and fourth MIS field effect transistors connected in series between the power supply line and ground; a capacitor connected between the gate and source of the third MIS field effect transistor, and; a fifth MIS field effect transistor connected between first and second nodes, the first node connecting the first and second MIS field effect transistors, and the gate of the third MIS transistor, the second node connecting the third and fourth MIS field effect transistors being connected to an output of the device, wherein a p-n junction portion which is connected to the capacitor is protected by a cover for preventing light from penetrating thereinto.

A lower member of a cross wire structure formed in a semiconductor device, such as an MIS type semiconductor memory device, is provided with a structure of at least two layers of an impurity-containing polycrystalline semiconductor material according to the method disclosed. These layers are connected in parallel and their resistance is thus decreased. Furthermore, since these layers may be formed within insulating films over a semiconductor substrate, the degree of integration of the semiconductor device may be enhanced. The method for producing the cross electrodes allows simultaneous fabrication of other semiconductor devices, for instance MIS devices with components commonly fabricated with the cross electrode structures.

Semiconductor device having cross wires

Disclosed is the addition of a capacitor circuit for augumenting the voltages at predetermined points in a sense amplifying circuit, in order to ensure a satisfactory refreshing of memory cells, since, if the potentials at the connecting points between a sense amplifying circuit and bit lines fall below a predetermined value when the sense amplifying circuit is caused to operate, it is difficult to achieve a complete refreshing of the memory cells.

Memory circuit

A semiconductor device has VMOS transistors and VMOS dynamic memory cells which are formed on the same semiconductor substrate of a first conductivity type. A buried layer of the opposite conductivity type is formed between the substrate and an epitaxial layer having V-grooves for the VMOS dynamic memory cells. In the buried layer are formed buried layers of the first conductivity type serving as sources and capacitors for the VMOS dynamic memory cells.

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Yokohama, Japan

Kiyoshi Miyasaka