Hitachi, Ltd.

Other

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Engineering Corp.

Hitachi Microcomputer System, Ltd.

Hitachi Vsli Engineering Corp.

Kiyoshi Matsubara

Masanao Sato

Hirofumi Mukai

Kenichi Kuroda

Kazuyoshi Shiba

Masaaki Terasawa

Shiro Baba

Takashi Ito

Naoki Yashiki

Eiichi Ishikawa

Yasushi Akao

Kouki Noguchi

Shumpei Kawasaki

Yasuyuki Saito

Naoki Yada

Atsushi Hasegawa

Keiichi Kurakazu

Hiroshi Ohsuga

Yoshitaka Ito

Akio Hayakawa

Kazufumi Suzukawa

Toshimasa Kihara

Naoki Mitsuishi

Tadashi Yamaura

Toshihiro Tanaka

Mitsuru Watabe

Yutaka Shinagawa

Takayuki Oshima

Masamichi Fujito

Shigeki Masumura

Kaoru Fukada

Eiji Sakakibara

Sonoko Abe

Isamu Mochizuki

Hideo Nakamura

Fumio Tsuchiya

Yoshiyuki Ozawa

Yoh Takamori

Kazuo Kato

Nobuaki Miyakawa

Yoshimune Hagiwara

Terumi Sawase

Makoto Aihara

Masaru Shibukawa

Norishige Kawashimo

A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein

A data processing apparatus supplied a first voltage from outside, includes a CPU, a first voltage generating circuit, a second voltage generating circuit, a clock generating circuit, and, a nonvolatile memory which can be accessed by the CPU. The first voltage generating circuit generates a second voltage, a voltage level of which is lower than that of the first voltage. The clock generating circuit is supplied the second voltage from the first voltage generating circuit and generates a clock signal, and the second voltage generating circuit is supplied the second voltage from the first voltage generating circuit and the clock signal from the clock generating circuit, and generates a second voltage, a voltage level of which is higher than that of the first voltage, for supplying to the nonvolatile memory.

Microcomputer and microprocessor having flash memory operable from single external power supply

A semiconductor processing device is provided which includes a nonvolatile memory unit, a voltage generating unit, and a first terminal. The voltage generating unit generates a first voltage generated from an operation voltage provided from outside of the semiconductor processing device and provides the first voltage to the nonvolatile memory unit for storing data therein. The first terminal provides the first voltage generated by the voltage generating unit to outside of the semiconductor processing device. This first voltage provided to outside of the semiconductor processing device via the first terminal permits checking a voltage level of the first voltage and correcting this voltage level.

A data processing apparatus having a built-in flash memory and being capable of rewriting the built-in flash memory by use of versatilely used PROM writer has a CPU, an electrically rewritable nonvolatile flash memory both formed in a single semiconductor substrate, and is operable in a mode in which the built-in flash memory is rewritable in accordance with commands supplied from a PROM writer. The data processing apparatus has a command latch made externally writable when the above-mentioned operation mode is established, a command analyzer and a sequence controller for controlling a sequence of rewriting the flash memory in accordance with the analysis result. The command analyzer and sequence controller may be realized by the CPU.

Data processing apparatus having a flash memory built-in which is rewritable by use of external device

A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.

Method for manufacturing a printed board on which a semiconductor device having two modes is mounted

A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory

Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements

Microcomputer including a flash memory that is two-way programmable

Growing community of inventors

Higashimurayama, Japan

Kiyoshi Matsubara