Freescale Semiconductor,inc.

Motorola Corporation

Qualcomm Incorporated

Kiyoshi Kase

Dzung T Tran

May Len

Susanne A Paul

Marius Goldenberg

Joseph Y Chan

Vladimir Koifman

Yachin Afek

Conor O'Keeffe

Paul M Astrachan

Paul Kelleher

David Yatim

Eliezer Sand

Chunhe Zhao

John E Angello

Satyavathi Akella

A directional coupler utilizes an inductive element of a power amplifier and a coupled conductive element. The inductive element of the power amplifier is a functioning element within the power amplifier and at least part of the inductive element of the power amplifier is disposed in a multi-layer substrate. At least part of the coupled conductive element is disposed in the multi-layer substrate. The coupled conductive element is configured to be inductively coupled to the inductive element of the power amplifier such that the coupled conductive element carries a first RF signal that is representative of a second RF signal within the inductive element of the power amplifier.

Integrated directional coupler within an RF matching network

A semiconductor device comprises sampling logic, comprising: input sample path selection logic arranged to enable at least one input sample path; sampler logic arranged to receive and sample an input data signal in a serial data stream in accordance with a phase of the at least one enabled input sample path; and transition detection logic arranged to detect transitions within the received input data signal. The input sample path selection logic is further arranged, upon detection of a transition within the received input data signal, to determine if the phase of the at least one input sample path is a phase having a largest window between logic values; and if it is determined that the phase of the at least one input sample path is not the phase having a largest window between logic values, to enable at least one input sample path comprising a more appropriate phase.

Method for sampling data and apparatus therefor

A current boost module receives a signal from the input and the output of a buffer to determine whether the buffer is transitioning between logic states. When the buffer is transitioning, a boost current is provided to a load connected to the buffer output to supplement the current from buffer output, thereby facilitating transition of a signal at the load. The current boost module can shut down the boost current before the signal at the load completes its transition from one logic state to the other.

Electronic device and method

An adaptive variable length pulse synchronizer including a state keeper circuit, an asynchronous pulse edge detection circuit, a data synchronization circuit, and a pulse edge synchronization circuit. The state keeper circuit detects a leading edge of the asynchronous pulse. The asynchronous pulse edge detection circuit detects a trailing edge of the asynchronous pulse after the state keeper circuit has detected the leading edge. The asynchronous pulse edge detection circuit further provides a pulse synchronized with a clock signal after the asynchronous pulse has been detected. The data synchronization circuit latches the asynchronous data and provides the synchronous data in response to the synchronous pulse. The pulse edge synchronization provides the synchronous ready signal after synchronous data has been provided. In one embodiment, the synchronous pulse occurs between successive rising edges of the clock whereas the synchronous ready signal is provided in response to the intermediate falling edge of the clock.

Adaptive variable length pulse synchronizer

Methods and corresponding systems for buffering an input signal include outputting a first logic value in response to the input signal being below a lower threshold. A second logic value is output in response to the input signal rising above the lower threshold. Thereafter, the second logic value is maintained until the input exceeds a higher threshold and thereafter falls below the higher threshold. In response to the input signal falling below the higher threshold, the first logic value is output, and maintained at the first logic value, until the input falls below the lower threshold and thereafter rises above the lower threshold.

Input buffer

An amplifier comprises an amplifier stage and an active inductor. The amplifier stage has an input terminal and an output terminal. The active inductor comprises first and second resistors and first and second transistors. The first resistor has a first terminal coupled to the output terminal of the amplifier stage, and a second terminal. The second resistor has a first terminal coupled to the output terminal of the amplifier stage, and a second terminal. The first transistor has a first current electrode coupled to the second terminal of the first resistor, a control electrode coupled to receive a bias voltage, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the second terminal of the second resistor, and a second current electrode coupled to a first power supply voltage terminal.

Amplifier with active inductor

A circuit's performance may vary based on various factors such as, for example, process, voltage, and/or temperature. In one embodiment, a circuit includes an input terminal which receives an input signal, a delay selection section which delays the input signal by a delay amount selected by a performance variation indicator, an impedance selection section which outputs the delayed input signal as a compensated delayed signal, where the impedance selection section uses a driver impedance amount selected by the performance variation indicator, and an output terminal which outputs the compensated delayed signal. The circuit may also include a ring oscillator, a frequency counter which provides a count value which indicates a number of rising edges of an output of the ring oscillator which occur during a period of a reference frequency, and a decoder which uses the count value to output the performance variation indicator.

Performance variation compensating circuit and method

In one form a circuit has a bias stage having an input signal terminal for receiving an input signal. The circuit modifies the input signal with a drive stage to provide an output signal in complement form. A drive transistor in the drive stage of the circuit has a bulk that is connected to a terminal of a load and to a control electrode coupled to the input signal terminal. A bias transistor in the bias stage of the circuit has a bulk that is directly connected to the terminal of the load and to the bulk of the drive transistor. The bias transistor has a control electrode coupled to the input signal terminal. The input signal biases the bulks of the drive transistor and the bias transistor and reduces transistor threshold voltage. Linearity of circuit output impedance is improved and RF interference reduced. Lower voltage operation is also provided.

Low voltage circuit with variable substrate bias

A voltage control circuit includes a first transistor coupled to a first voltage supply terminal having a first voltage, a second transistor coupled to the first transistor and a node, a third transistor coupled to a second voltage supply terminal and the node, wherein the second voltage supply terminal has a second voltage and the node is at a voltage selected from the group consisting of the first voltage and the second voltage, and a fourth transistor coupled to the node.

Voltage control circuit having a power switch

An input buffer circuit with hysteresis includes a first stage and a second stage. The first stage includes a resistive device to provide a resistance between two nodes of the first stage. The two nodes are responsive to a signal input. The second stage includes four series-coupled transistors. A first node is coupled to the control electrodes of two of the four transistors and the second node is coupled to the control electrodes of the other two transistors. The second stage includes a signal output. In some examples, a resistance provided by the resistive device is variable and provides the buffer circuit with hysteresis.

Latching input buffer circuit with variable hysteresis

An input voltage circuit comprises an input transistor having a control electrode for receiving a variable input voltage, a voltage detection transistor having a current electrode coupled to a current electrode of the input transistor forming a first node, and a current source coupled to a second current electrode of the voltage detection transistor forming a second node. The input voltage circuit further comprises a variable voltage drop transistor having a first current electrode coupled to the first node, a control electrode coupled to the second node and a second current electrode coupled to an output node, wherein the voltage detection transistor detects a variation in the variable input voltage and provides a signal to the variable voltage drop transistor. The variable voltage drop transistor generates a voltage drop proportional to the variation in the variable input voltage to ensure a substantially constant output at the output node.

Input circuit for receiving a variable voltage input signal and method

A voltage regulator includes a first and second amplifier stage, an output stage, and a variable zero circuit. The first amplifier stage is coupled to receive a reference voltage and introduces a first pole of the voltage regulator. The second amplifier stage is coupled to the first amplifier stage and introduces a second pole of the voltage regulator. The output stage is coupled to the second amplifier stage, has an output driver, and is coupled to provide an output voltage based on the reference voltage. The variable zero circuit is coupled to the first amplifier stage, the second amplifier stage, and the output stage. The variable zero circuit provides a zero to compensate for at least one of the first pole or the second pole of the voltage regulator based on a gate to source voltage of the output driver and a drain to source voltage of the output driver.

Voltage regulator with adaptive frequency compensation

A circuit and a method for interpolative delay is provided. The circuit includes a delay locked loop with interpolation delay. The delay locked loop includes a differential inverter, an interpolation circuit, and a differential compare circuit. The differential inverter is coupled to receive a differential clock signal and coupled to provide an inverted differential clock signal. The interpolation circuit is coupled to receive both the clock signal and the inverted clock signal, and to provide an interpolated clock signal having a first delay relative to the clock signal. The differential compare circuit is coupled to receive the inverted clock signal and coupled to provide a non-interpolated clock signal having a second delay relative to the clock signal. The second delay corresponds to a full delay of the differential inverter and the first delay corresponds to a predetermined fraction of the full delay.

Circuit and method for interpolative delay

A well bias module outputs a voltage used to bias the wells of transistors or other semiconductor components. The well bias module includes a feedback loop having a voltage generation module and a subthreshold leakage sense module that is operable to model the transistors or other semiconductor components so as to sense the subthreshold leakage resulting from a particular well bias voltage output by the voltage generation module. The subthreshold leakage sense module provides a representation of the sensed subthreshold leakage to the voltage generation module, which adjusts the magnitude of the well bias voltage based on this representation so as to reduce or minimize the subthreshold leakage in the transistors or other semiconductor components.

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Austin, TX, United States of America

Kiyoshi Kase