Nec Corporation

Ricoh Company, Ltd.

Nec Electronics Corporation

Adv Antest Corporation

Kiyoshi Fukushima

Takashi Miyazaki

Junichi Sasaki

Kenji Hashimoto

Yukio Maehashi

Kazuo Murai

Hajime Sakuma

Hiroshi Honmou

Masataka Itoh

Isao Yoneda

Sumio Suzuki

Hisaharu Oba

In an one-chip microcomputer used in an automobile, error correction code data is added to corresponding user data, and then the resulting user data is stored into an EEPROM to correct an 1-bit error contained in this user data. The one-chip microcomputer is arranged by an electrically erasable memory for temporarily storing thereinto externally supplied user data and ECC (error correction code) data corresponding to the user data; a program storage memory for previously storing thereinto a program; and a CPU (central processing unit) for reading the program from the program storage memory so as to produce the ECC data based upon the externally supplied user data, and for sequentially correcting errors contained in the externally supplied user data by using the produced ECC data corresponding to the externally supplied user data.

One-chip microcomputer capable of internally producing ECC data

Herein disclosed is a semiconductor device simulation apparatus which is set the various parameters to be used for measuring a current value and a voltage value that varies depending on the internal resistance of a DUT, and simulates a current value or a voltage value that varies depending on an internal resistance of a DUT in accordance with various parameters and a prescribed test signal when receiving the test signal. Also disclosed is a semiconductor test program debugging apparatus using such a semiconductor device simulating apparatus.

Semiconductor device simulating apparatus and semiconductor test program debugging apparatus using it

A light receiving element is comprised of a light sensitive surface on a semiconductor substrate and a positive electrode (anode), a negative electrode (cathode), a mounting precision test mask, a conductive electrode wire, and solder resist on the same substrate surface. A metal thin film, a mounting alignment mark, and a mounting precision mark window are provided on the back side of the substrate. Two or more electrode surfaces having either the anode or the cathode used as the common electrode are provided. The light sensitive surface is positioned approximately in the center between these two electrode surfaces. A highly precise mounting can therefore be achieved with the solder bump, even when mounting single light receiving elements. High precision mounting is also obtained when mounting light receiving element arrays. This type of light receiving element can be precisely positioned and bonded by solder bumps to a substrate having an optical fiber fitted in the V groove.

Light receiving device for use in optical fiber communications and the

In order to provide an input circuit for mode setting with a simple configuration sufficiently stable and without unnecessary current consumption, the input circuit of the invention, for outputting a control signal (MODE OUT) according to a status of a mode setting terminal (I1), comprises latch means (100) being reset with a rising edge of a reset signal (RES) to output the control signal (MODE OUT) of logic LOW and latching logic of the mode setting terminal (I1) with a falling edge of a delayed signal (RESD) of said reset signal (RES) for maintaining to output inverse or the same logic of said logic of the mode setting terminal (I1) latched, and pull-up or pull-down means (P1) becoming ON for pulling up or down the mode setting terminal (I1) to logic HIGH or LOW when the mode setting terminal (I1) is left open gated by logic LOW of the control signal (MODE OUT) and becoming OFF for cutting a current flowing through the mode setting terminal (I1) gated by logic HIGH of the control signal (MODE OUT).

Input circuit for mode setting

An erasable programmable read-only memory (EPROM) includes a plurality of EPROM cells arranged in a matrix having a plurality of rows and a plurality of columns, and a plurality of digit lines each connected in common to drains of the EPROM cells included in a corresponding one column of EPROM cells. A Y-selector receives a Y-address of a given address for selecting one digit line of the digit lines so as to connect the selected digit line to a sense amplifier. Each of the digit lines is connected to one of reading-inhibition circuits having a reading-inhibition information storing EPROM cell, so that when the reading-inhibition information storing EPROM cell of the reading-inhibition circuits are in a written condition, the digit line is forcibly maintained at a predetermined logic level. The EPROM can inhibit the reading of any bit or bits and any area of an EPROM.

Memory protection circuit for EPROM

A programmable read only memory device comprises a first memory unit for data codes, a second memory unit for parity codes, and an error checking and correction unit for retrieving an original data code from the data code and the associated parity code, wherein a test data code and an improper or proper parity code is supplied from a test data register to the error checking and correction unit so that not only the data checking circuit but also the data correction circuit are examined to see if or not any trouble takes place therein.

Programmable read only memory device having test tool for error checking

Disclosed herein is a microcomputer having a test circuit for an A/D converter of a C/R type. This converter includes a resistor circuit having a plurality of resistors connected in series between reference potential points to generate a changeable reference voltage and a capacitor circuit having a plurality of capacitors for storing electrical charges relative to an analog input voltage and to the changeable reference voltage, and the test circuit is coupled to the resistor circuit and the capacitor circuit and further to first and second terminals and activated in a test mode to transfer the changeable reference voltage to the first terminal and another reference voltage, which is produced outside the microcomputer, to the capacitor circuit.

Microcomputer having test circuit for A/D converter

A CPU includes a program counter, an execution unit, and a program status word register. A pulse producing unit connected to the CPU includes a plurality of output terminals, a port selection register for designating at least one of the output terminals, and a system for generating a pulse start timing signal, a system responsive to the pulse start timing signal for bringing the designated output terminal into one of two bistable logic states. A counter counts a clock pulse signal and brings the selected output terminal into the other of the bistable logic states when the counter indicates a predetermined elapsed time. Another system responsive to the pulse start timing signal sends a signal to the CPU requesting a macro service operation. A system responsive to the request of the macro service operation suspends the program being executed, and a system performs the macro service operation, without saving the contents of the program counter and the program status word register into the data memory and while holding the contenst thereof as they are. The program being executed is resumed after the macro service operation has ben completed. The pulse producing unit may be coupled to a fuel injection device in an engine unit, and may have an input terminal for receiving a pulse request signal from the engine unit.

Data processing apparatus for producing in sequence pulses having

An automatic control system for an offset printing machine includes a process execution instructions generating circuit having latched therein instructions for executing various operation processes and adapted to shift from one operation phase to another for successively generating process execution instructions, so that an ink forming and master plate feeding process, an inking process, a transfer-printing process, a printing process, and a master plate ejecting and cleaning process can be automatically executed in correct order. The number of times for executing each of the etching, inking, transfer-printing and cleaning processes can be adjusted in a process setting structure. When a master plate feeding error detecting signal is generated, the process execution instructions generating circuit is reset to an initial condition of stop instructions which prevailed prior to actuation of a start switch. When a master plate ejection error signal or other misoperation indicating signal is generated, the process execution instructions generating circuit remains latched to the current operation process, and a lamp is lighted to indicate the process in which misoperation has occurred. The period of time for moistening an etching roller can be determined depending on the number of copies to be produced. The control system allows the offset printing machine to manually execute any operation process or processes as desired.

Growing community of inventors

Tokyo, Japan

Kiyoshi Fukushima