Mitsubishi Electric Corporation

Mitsubishi Denki Kabushiki Kaisha

Alstom Transport Sa

Fuji Jukogyo Kabushiki Kaisha

Daiichi Sankyo Company, Limited

Kiyoshi Arai

Gourab Majumdar

Makoto Mizuno

Satoru Ishikawa

Yasunari Hino

Emmanuel Dutarde

Pierre Solomalala

Jose Saiz

Benoit Boursat

Philippe Lasserre

Makoto Kondou

Yoshio Takagi

Nobuhisa Honda

Osamu Usui

Shinsuke Asada

Hideo Matsumoto

Shohei Ogawa

Tatsuya Iwasa

Yuki Yano

Tsuyoshi Homma

Yoshimitsu Tateno

Tetsuo Fukagawa

Yumie Kitajima

Kenichi Kanazawa

Katsuharu Morioka

Tatunori Yanagimoto

Yutaka Ohtsuka

Hirofumi Omachi

Majumdar Gourab

Tatuya Iwasa

Mitsugu Sakai

An object is to provide a semiconductor device which suppresses poor bonding between a metal pattern and an electrode terminal due to insufficient temperature rise at the time of bonding the metal pattern and the electrode terminal. The electrode terminal is branched into a plurality of branch portions in a width direction on one end side of an extending direction thereof, of the plurality of branch portions, a first branch portion and a second branch portion are bonded on the metal pattern via a bonding material, respectively, the first branch portion has a wider width than that of the second branch portion, and the bonding material between the second branch portion and the metal pattern is thinner than the bonding material between the first branch portion and the metal pattern.

Semiconductor device with branch electrode terminal and method of manufacturing semiconductor device

An object of the present invention is to obtain a semiconductor device having highly reliable bonding portions. The semiconductor device according to the present invention includes an insulating substrate on which a conductive pattern is formed, and an electrode terminal and a semiconductor element which are bonded to the conductive pattern, the electrode terminal and the conductive pattern are bonded by ultrasonic bonding on a bonding face, and the ultrasonic bonding is performed at a plurality of positions.

Semiconductor device manufacturing method comprising bonding an electrode terminal to a conductive pattern on an insulating substrate using ultrasonic bonding

In a power semiconductor device, an IGBT has a collector electrode bonded to a metal plate by a bonding material. A diode has a cathode electrode bonded to the metal plate by the bonding material. An interconnection member is bonded to an emitter electrode of the IGBT by a bonding material. The bonding material includes a bonding material and a bonding material. The bonding material is interposed between the IGBT and the interconnection member. The bonding material fills a through hole formed in the interconnection member. The bonding material reaches the bonding material and is therefore connected to the bonding material.

Power semiconductor device and method for manufacturing same

A pharmaceutical for the prophylaxis or treatment of hypertension or a disease derived from hypertension. The pharmaceutical is characterized by comprising (i) a specific mineralocorticoid receptor antagonist and (ii) one or more components selected from the following components (A) to (C), for administration simultaneously or separately at a time interval: (A) an angiotensin II receptor antagonist, (B) a calcium antagonist, and (C) a diuretic.

Pharmaceutical for prophylaxis or treatment of hypertension

A semiconductor device according to the present invention includes a base plate, an insulating layer provided on an upper surface of the base plate, a metal pattern provided on an upper surface of the insulating layer, a semiconductor element bonded to the metal pattern, and an insulating substrate disposed to be in contact with an upper surface of the semiconductor element. An end of the insulating substrate is located outside the semiconductor element in plan view. The end of the insulating substrate and the metal pattern are directly or indirectly bonded. The semiconductor element includes an electrode on the upper surface. A portion of the insulating substrate, in which the electrode on the upper surface of the semiconductor element overlaps in plan view, is provided with a through-hole.

Semiconductor device

A P-side package unit and a N-side package unit are arranged on a main surface of a metal heatsink such that a main surface extends in a direction perpendicular to the main surface of the heatsink. Each of the P-side package unit and the N-side package unit is fixed by an end edge portion of a heatsink being clipped by a rail-shaped unit mounting part provided on the main surface of the heatsink.

Semiconductor device module

A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Semiconductor module including a switch and non-central diode

A semiconductor device includes a semiconductor element and a connector. The semiconductor element has a power device of a voltage drive type for controlling an on operation and an off operation of a main current by input of a drive signal. The connector receives the drive signal without making contact with an issuing unit issuing the drive signal, and transmits the drive signal to the semiconductor element. The semiconductor element preferably includes a control unit for converting the drive signal received by the connector into a voltage value, and transmitting the voltage value to the semiconductor element.

An FOM (figure of merit) enabling evaluation from a cost aspect, as well as evaluation of electrical performance, is newly proposed to provide a method of manufacturing based on the FOM a semiconductor chip intended for a lower cost production in addition to satisfying electrical performance. An FOMof a semiconductor chip is defined as the product of a term represented by electrical performance of a substrate S and a term represented by a semiconductor chip cost C; the FOMof each of the semiconductor chips on substrates S, Sof different type is determined by calculation of the product thereof. Based on the magnitudes of the calculation results, a desired substrate is selected from the substrates S, Sand then a semiconductor chip is fabricated by forming a semiconductor element on the desired substrate selected.

Method of manufacturing semiconductor chip and semiconductor module

The present invention relates to a power semiconductor device comprising a switching power semiconductor element, and a free wheeling diode in anti-parallel connection to the switching power semiconductor element. The power semiconductor is characterized in that a reverse electrode of the switching power semiconductor element and a reverse electrode of the free wheeling diode are bonded and mounted on a circuit pattern formed on the main surface of the first substrate, and that a circuit pattern, which is so formed on the main surface of the second substrate as to oppose a surface electrode of the switching power semiconductor element and a surface electrode of the free wheeling diode, is connected to the surface electrodes of the switching power semiconductor element and the free wheeling diode through connective conductors to be soldered, respectively.

Power semiconductor device

One of the aspects of the present invention is to provide a power semiconductor device, including a first substrate having a first circuit pattern formed thereon, and a second substrate having a second circuit pattern formed thereon. The first substrate has a first center line extending along a predetermined transverse direction. At least one power semiconductor chip is mounted on the first circuit pattern of the first substrate, and has at least one chip electrode opposing to the second circuit pattern of the second substrate. Also, a plurality of first conductive connectors on the first circuit pattern is provided for electrical connection with the second circuit pattern of the second substrate. The first conductive connectors are arranged symmetrically in relative to the first center line of the first substrate.

Arrangement of conductive connectors in a power semiconductor device

A power semiconductor device includes a portion and an external package enclosing the portion. The portion includes a ceramic board sides provided on the ceramic board defining a space filled with a thermal insulator, and a silicon carbide power semiconductor element enclosed within the thermal insulator. The external package is made of a material having a thermal conductivity lower than that of the side.

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Tokyo, Japan

Kiyoshi Arai