Hitachi, Ltd.

Kiyoo Ito

Ryoichi Hori

Takao Watanabe

Katsutaka Kimura

Masahiro Iwamura

Goro Kitsukawa

Ikuro Masuda

Hideo Sunami

Kazuo Nakazato

Kunihiko Yamaguchi

Noriyuki Honma

In the case of a large capacity DRAM (Dynamic Random Access Memory) of a conventional type, since a signal voltage read out from a memory cell is low, the action thereof is apt to be unstable. If a gain is added to a memory cell to obtain a large output voltage, the area for a memory cell becomes large. Accordingly, a memory cell with RAM action being stable and which requires a small area is needed. A memory cell according to the present invention is provided with MOS transistors to read out storage information, transistors and to write storage information, and a capacitor to control the voltage at the storage node. These component parts are assembled to form a 3-dimensional structure.

Semiconductor device

A dynamic random access memory device is provided having a dynamic memory cell, a word line coupled to the dynamic memory cell, a data line coupled to the dynamic memory cell, a precharge circuit coupled to the data line, a word driver coupled to the word line and a decoder coupled to the word driver. A plurality of address lines coupled to the decoder. The decoder has a first logic circuit whose inputs are connected to the plurality of address lines. The decoder also has a latch circuit whose input is connected to an output of the first logic circuit and whose output is connected to the word line.

Dynamic random access memory having bipolar and C-MOS transistor

In a monolithic storage device having bit lines to which a plurality of memory cells are connected, and I/O lines which connect an external data input/output terminal and the bit lines and which exchange data between the input/output terminal and the bit lines; the improvement wherein said bit lines are divided into a plurality of groups each having the I/O lines, and a deserializer circuit is disposed between said each I/O line and an input terminal.

Monolithic storage device

In a semiconductor memory device including memory and dummy cells connected to groups of data lines, word lines and dummy word lines for selecting the memory and dummy cells, respectively, and a signal detector for differentially amplifying the read signal from the memory cell selected by the signal of the word line and a reference signal from the dummy cell, the improvement wherein the memory cell capacitor consists of two capacitors, each having substantially the same structure as a dummy cell capacitor and connected in parallel with the other.

Semiconductor memory device having a dummy cell and a memory cell which

Growing community of inventors

Higashikurume, Japan

Kiyoo Ito