Hitachi, Ltd.

Other

Elpida Memory, Inc.

Agency of Industrial Science and Technology

Hitachi Ulsi Systems Co., Ltd.

Kiyonori Ohyu

Masahiro Moniwa

Kozo Watanabe

Atsushi Ogishima

Kenichi Kuroda

Masayuki Kojima

Yasuo Wada

Nobuyoshi Natsuaki

Syunichi Hashimoto

Nozomu Matsuda

Kensuke Okonogi

Masao Tamura

Masashi Horiguchi

Norio Hasegawa

Yoshitaka Tadaki

Makoto Ohkura

Aritoshi Sugimoto

Eiichi Murakami

Masanobu Miyao

Shinichi Fukada

Makoto Ogasawara

Tadashi Suzuki

Satoru Yamada

Shoji Shukuri

Hiroyuki Ohta

Kazuyoshi Oshima

Takashi Ohshima

Osamu Tsuchiya

Yoshifumi Kawamoto

Atsushi Hiraiwa

Takashi Nishida

Terunori Warabisako

Kiyokazu Nakagawa

Kazutaka Manabe

Takuo Ohashi

Kazuo Ogawa

Hidekazu Okuhira

Akira Shintani

Yuuichi Madokoro

Keiichi Watanabe

Toshihiro Imamura

Msao Tamura

Shoji Syukuri

A semiconductor device may include, but is not limited to, a single crystal silicon diffusion layer, a polycrystal silicon conductor, and a diffusion barrier layer. The diffusion barrier layer separates the polycrystal silicon conductor from the single crystal silicon diffusion layer. The diffusion barrier layer prevents a diffusion of at least one of silicon-interstitial and silicon-vacancy between the single crystal silicon diffusion layer and the polycrystal silicon conductor.

Semiconductor device and method of forming the same

A method for manufacturing a DRAM device on a silicon substrate includes: forming cell transistors in a memory cell area and other transistors in a peripheral circuit area; forming polysilicon plugs connected to diffused regions of the cell transistors and metallic plugs connected to diffused regions of the other transistors; heat treating at a temperature of 980 to 1,020 degrees C.; heat treating at a temperature of 700 to 850 degrees C.; implanting fluorine or boron fluoride into the diffused regions of the other transistors; and heat treating at a temperature of 500 to 850 degrees C.

Method for manufacturing a semiconductor device having polysilicon plugs

In a method for manufacturing a semiconductor device having a laminated gate electrode, a phosphorus-doped polysilicon is formed on a gate oxide film. A high-melting metal or a compound of a high-melting metal and silicon is formed on the polysilicon. Phosphorus is doped into the polysilicon so that a concentration of the phosphorus in the polysilicon at an interface between the polysilicon and the gate oxide film is 2&#xd7;10(1/cm) or less. Then, thermal oxidation is carried out in a wet-hydrogen atmosphere containing water vapor.

Method of fabricating a semiconductor device having a decreased concentration of phosphorus impurities in polysilicon

A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodesare formed via a gate insulating filmon the main surface of a semiconductor substrate, and on side surfaces of each of the gate electrodes there is formed a first side wall spacercomposed of silicon nitride and a second side wall spacercomposed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holesandin a self-matching manner with respect to the first side wall spacersand connecting portion is formed connecting a conductorto a bit line BL. In addition, in the N channel MISFETs Qnand Qn, and in the P channel MISFET Qpin areas other than the DRAM memory cell area, high density N-type semiconductor areasandare formed, as well as a high density P-type semiconductor areais formed in a self-matching manner with respect to the second side wall spacers

Semiconductor integrated circuitry and method for manufacturing the circuitry

A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes are formed via a gate insulating film on the main surface of a semiconductor substrate , and on side surfaces of each of the gate electrodes there is formed a first side wall spacer composed of silicon nitride and a second side wall spacer composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes and in a self-matching manner with respect to the first side wall spacers and connecting portion is formed connecting a conductor to a bit line BL. In addition, in the N channel MISFETs Qn and Qn , and in the P channel MISFET Qp in areas other than the DRAM memory cell area, high density N-type semiconductor areas and are formed, as well as a high density P-type semiconductor area is formed in a self-matching manner with respect to the second side wall spacers

In a semiconductor integrated circuit device having a memory cell which includes a MIS.FET and a capacitance element, the conductivity type of a low-resistance polysilicon film which constitutes the gate electrode ( ) of the memory cell selecting MIS.FET (Q) of n-channel type constituting the memory cell is set at p -type in order to enhance the refresh characteristics of the memory cell.

Semiconductor integrated circuit device and the method of producing the same

A field oxide film in a region where relief cells are formed is made wider than the field oxide film in a region where normal memory cells are formed thereby to make a field relaxation layer of the relief cells deeper than the field relaxation layer of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.

Semiconductor integrated circuit device and process for manufacturing the same

It is an object of the present invention to provide a technology of a semiconductor integrated circuitry that allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operated faster. In a method for manufacturing such a semiconductor integrated circuitry of the present invention, at first, gate electrodes are formed via a gate insulating film on the main surface of a semiconductor substrate , and on side surfaces of each of the gate electrodes is formed the first side wall spacer composed of silicon nitride and the second side wall spacer composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area are opened connecting holes and in a self-matching manner with respect to the first side wall spacers and are formed connecting portion connecting a conductor to a bit line BL. In addition, in the N channel MISFETs Qn and Qn , and in the P channel MISFET Qp in areas other than the DRAM memory cell area are formed high density N-type semiconductor areas and , as well as a high density P-type semiconductor area in a self-matching manner with respect to the second side wall spacers

Semiconductor integrated circuit device and method for manufacturing the same

A field oxide film,in a region where relief cells are formed is made wider than the field oxide film,in a region where normal memory cells are formed thereby to make a field relaxation layer,of the relief cells deeper than the field relaxation layer,of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.

An arrangement is provided to decrease the junction degradation caused by the leakage current at a p-n junction in semiconductor devices. This arrangement can be useful for a variety of devices, and is especially effective for reducing junction degradation at the source or drain region of a MOSFET. To achieve such a reduction, a p-n junction layer is provided at a p-n junction of a semiconductor region and a substrate. Carrier concentration distributions of a p-type layer and an n-type layer of the p-n junction layer are set so that an electric field which tends to be increased by a local electric field enhancement in a depletion layer of the p-n junction due to a precipitate introduced from a semiconductor surface will not exceed 1 MV/cm. When the depth of a depletion layer of the p-type layer or the n-type layer is referred to as Xp or Xn, and the slope of the carrier concentration, Ap or An, the following relation is provided:

Semiconductor device including arrangement for reducing junction

A method of producing a hetero structure, including the steps of depositing hydrogen atoms or halogen atoms onto a surface of a first single crystal layer formed of semiconductor or metal silicide, and forming a second single crystal layer on the first single crystal layer by hetero epitaxial growth, the second single crystal layer being formed of semiconductor or metal silicide different from the material of the first single crystal layer, wherein both of the steps are continuously conducted without taking the hetero structure out of a producing device. Further, the number of the hydrogen atoms or the halogen atoms to be deposited is equal to or in the range of .+-.50% with reference to the number of dangling bonds existing in a hetero interface between the first single crystal layer and the second single crystal layer, so that the lattice defects in the hetero interface can be reduced.

Method of producing hetero structure

Of an amorphous Si film, a region to be formed into a lowly doped region such as the channel region of an MOS transistor is covered with a mask and an uncovered region is doped with an impurity. After this, the amorphous Si film is annealed and turned to signal crystal through solid phase epitaxial growth, and the mask itself is used as the electrode of a semiconductor device. By this impurity doping, a large-sized single-crystal Si film can be formed, and the impurity doping can be conducted in self-alignment with the electrode formation to produce a highly integrated semiconductor circuit.

SOI process for forming a thin film transistor using solid phase epitaxy

A desired portion of a refractory metal silicide film is oxidized by anodic oxidation to form oxides of silicon and of metal. The oxides formed are completely removed by etching. By so doing, the desired portion of the silicide film can be etched selectively without badly damaging an underlying silicon substrate or silicon dioxide film. Therefore, it is possible to easily affect patterning of the silicide film used for electrodes of MOS transistors and bipolar transistors as well as resistors and interconnections.

Method of fabricating a semiconductor device including selective etching

First conductivity type impurity ions are implanted at a predetermined depth all over a region where impurity ions are to be implanted, and second conductivity type impurity ions are implanted in a dose about twice as large as that of the first conductivity type impurity ions at substantially the same implantation depth of the first conductivity type impurity ions, followed by annealing. In this way, mutually contiguous first and second conductivity type regions having substantially the same impurity concentrations and located at substantially the same depths are formed.

Method of forming twin doped regions of the same depth by high energy

Growing community of inventors

Tokyo, Japan

Kiyonori Ohyu