Kabushiki Kaisha Toshiba

Kioxia Corporation

Kiyomi Naruke

Seiji Yamada

Hiroshi Watanabe

Tomoko Suzuki

Masamitsu Oshikiri

Etsushi Obi

Kazunori Masuda

Shinichi Maekawa

Tutomu Tamaki

Fumitaka Arai

Hideo Kato

Junichi Miyamoto

Hirofumi Inoue

Shinichiro Shiratake

Hiroaki Tsunoda

Mutsumi Okajima

Hidetoshi Saito

Kuniyoshi Yoshikawa

Shigeo Kondo

Naoyuki Shigyo

Mutsuo Morikado

Eiji Sakagami

Yuuichi Tatsumi

Tohru Maruyama

Takamichi Kasai

Hidefumi Nawata

Hiroyuki Sasaki

Katsuto Katoh

Yasumasa Sawada

Minoru Kurata

A device includes a stack above a substrate in a first direction perpendicular to a surface of the substrate, the stack including conductive layers; a semiconductor layer neighboring the stack in a second direction parallel to the surface of the substrate; a memory layer between the first stack and the semiconductor layer; memory cells between the conductive layers and the semiconductor layer; a first transistor connected between one end of the semiconductor layer in a third direction parallel to the surface of the substrate and crossing the second direction and a first interconnect in the first direction; and a second transistor connected between the other end of the semiconductor layer and a second interconnect in the first direction.

Memory device with transistors above memory stacks and manufacturing method of the memory device

A nonvolatile semiconductor memory device according to one embodiment includes: memory cells; word lines connected to the memory cells; and a control circuit configured to control a data read operation. When controlling the data read operation, the control circuit applies one of read voltages to a selected word line, applies a first read pass voltage to a first non-selected word line connected to one of data-written memory cells, and applies a second read pass voltage to a second non-selected word line connected to a non-written memory cell. Each of the read voltages is set to a voltage between two threshold voltage distributions. The first read pass voltage is set so that the data-written memory cells become conductive. The second read pass voltage is set so as to be lower than a highest read voltage, the highest read voltage being the highest voltage among the read voltages.

Nonvolatile semiconductor memory device

A memory system includes: a memory chip group including n chips of a nonvolatile semiconductor memory dividedly managed for each of unit areas having predetermined sizes, an unit area of one chip among the n chips storing an error correction code for a group including unit areas in the other n&#x2212;1 chips associated with the unit area, and the chip that stores the error correction code being different for each of positions of the unit areas; and an access-destination calculating unit that designates, when data in the unit areas is rewritten, the unit area in which the error correction code of data is stored as a writing destination of rewriting data, and designates an unit area in which data before rewriting is stored as a storage destination of a new error correction code.

Memory system and computer system

A non-volatile memory of a semiconductor device has a tunnel insulation film provided on the active area; a floating gate electrode provided on the tunnel insulation film; a control gate electrode provided over the floating gate electrode; and an inter-electrode insulation film provided between the floating gate electrode and the control gate electrode, wherein, in a section of the non-volatile memory cell in a channel width direction, a dimension of a top face of the active area in the channel width direction is equal to or less than a dimension of a top face of the tunnel insulation film in the channel width direction, and the dimension of the top face of the tunnel insulation film in the channel width direction is less than a dimension of a bottom face of the floating gate electrode in the channel width direction.

Semiconductor device and method for manufacturing the same

In a data erasing method of a nonvolatile semiconductor memory device, cells are subjected to the processings of executing programming by applying a voltage to the cells to set their threshold values at a given level or more, erasing the cells to set their threshold values at a lower level or less, executing weak programming once on a cell whose threshold value is lower than a further lower level, by applying a lower voltage to the cell, repeating the weak programming on the cell when its threshold value is still lower than the further lower level, until the value reaches the further lower level or more, verifying whether a cell is present whose threshold value is higher than the lower level, and returning the processing to the processing of setting the threshold values of the cells at the lower level or less, when verifying that the above cell is present.

Nonvolatile semiconductor memory device which erases data in units of one block including a number of memory cells, and data erasing method of the nonvolatile semiconductor memory device

Disclosed is a semiconductor device comprising a first transistor and a second transistor formed on a semiconductor substrate, wherein a gate side wall of the second transistor has a thickness equal to that of a gate side wall of the first transistor, wherein each of the first and second transistors has an inner low impurity diffusion region and an outer high impurity diffusion region, and wherein the size of the inner low impurity diffusion region of the second transistor along the surface of the semiconductor substrate is larger than that of the inner low impurity diffusion region of the first transistor.

Semiconductor device and method of manufacturing the same

There is disclosed a memory cell which has a diffusion layers constituting source/drain areas formed on a p-type silicon substrate surface, and a channel area formed between the diffusion layers. Above the channel area, an insulating film of a laminated structure is formed of a silicon oxide film, a silicon nitride film and a silicon oxide film. A gate electrode is formed on the upper surface of the insulating film of the laminated structure. The gate electrode is used as a word line. Moreover, an interlayer insulating film is formed between the diffusion layer and the gate electrode. By injecting hot electrons from the substrate to the silicon nitride film in the insulating film of the laminated structure, data is written. The silicon nitride film and the diffusion layer are partially overlapped in a vertical direction, and an offset portion is disposed between the silicon nitride film and the diffusion layer.

Method for manufacturing a semiconductor memory device with a fine structure

Semiconductor memory device, method for manufacturing the same, and

A method for manufacturing a semiconductor device having N-type source and drain regions formed substantially in parallel to each other in the surface of a P-type semiconductor substrate. A channel region having first to fourth edges are sandwiched between each pair of the source and drain regions on the first and second edges. A gate insulating film is formed on the semiconductor substrate. Gate electrodes are formed substantially in parallel to each other on the semiconductor substrate via gate insulating film so as to cross the source and drain regions. The first and second edges of the channel regions are substantially parallel to the source and drain regions, and third and fourth regions are substantially parallel to the gate electrodes. A P-type impurity diffusion region is formed by ion implantation in accordance with self-alignment with gate electrodes, at least on either side of the third and fourth edge of at least one of the channel regions. An impurity concentration of the impurity diffusion region is adjusted such that it is higher than that of the semiconductor substrate.

Method for manufacturing a semiconductor device having an adjustable

The present invention discloses a nonvolatile semiconductor memory device having a memory cell transistor in which an offset region is provided as a charge carrier injecting region. An insulating film and a gate electrode is formed in order of mention on a semiconductor substrate. Source/drain regions are formed on the surface of the semiconductor substrate with the gate electrode interposed therebetween. The drain has an LDD (Lightly Doped Drain) structure. Furthermore, a layered film of silicon oxide films and a SiN film is provided on a channel region between an edge of the gate electrode and a source diffusion layer. To be more specific, the layered film is formed in such a way that the SiN film is interposed between the silicon oxide films, constituting a side wall of the gate electrode. The SiN film is a charge carrier accumulating layer. Contact holes are formed in an insulating film between layers, respectively reaching the source and drain regions. Each of the contact holes are filled with a conductive material (contact plug). A conductive barrier film (diffusion protecting film) is provided on the bottom and to the inner wall portions of the contact hole. The contact plugs respectively connect the source and the drain to upper layer, aluminium wiring.

Nonvolatile semiconductor memory device having memory cell transistor

In this invention, charges are extracted from the charge storage portion by means of F-N tunnel current, and then avalanche hot carriers are injected into the storage portion.

Semiconductor memory device having data erasing mechanism

A semiconductor device having N-type source and drain regions formed substantially in parallel to each other in the surface of a P-type semiconductor substrate. A channel region having first to fourth edges are sandwiched between each pair of the source and drain regions on the first and second edges. A gate insulating film is formed on the semiconductor substrate. Gate electrodes are formed substantially in parallel to each other on the semiconductor substrate via gate insulating film so as to cross the source and drain regions. The first and second edges of the channel regions are substantially parallel to the source and drain regions, and third and fourth regions are substantially parallel to the gate electrodes. A P-type impurity diffusion region is formed by ion implantation in accordance with self-alignment with gate electrode, at least on either of the third or fourth edge of at least one of the channel regions. An impurity concentration of the impurity diffusion region is adjusted such that it is higher than that of the semiconductor substrate.

Semiconductor device with adjustable channel width

Growing community of inventors

Sagamihara, Japan

Kiyomi Naruke