Nec Corporation

Renesas Electronics Corporation

Nec Electronics Corporation

Kiyokazu Ishige

Hitoshi Nakamura

Kazuhiko Sanada

Kenji Saitou

Hiroshi Tsuda

Yoshitaka Kubota

Takuji Onuma

Hiromichi Takaoka

Kenichi Hidaka

Toshikatsu Jinbo

Shinichi Kawai

Noriaki Kodama

Akira Yoshino

Atsunori Miki

Kazuhisa Ninomiya

Teiichiro Nishizaka

Motoko Tanaka

Tomohiro Hamajima

Isami Sakai

A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer.

Semiconductor device having memory unit, method of writing to or reading from memory unit, and semiconductor device manufacturing method

An antifuse whose internal written information cannot be analyzed even by utilizing methods to determine whether there is a charge-up in the electrodes. The antifuse includes a gate insulation film, a gate electrode, and a first diffusion layer. A second diffusion layer is isolated from the first diffusion layer by way of a device isolator film, and is the same conduction type as the first diffusion layer. The gate wiring is formed as one integrated piece with the gate electrode, and extends over the device isolator film. A common contact couples the gate wiring to the second diffusion layer. The gate electrode is comprised of semiconductor material such as polysilicon that is doped with impurities of the same conduction type as the first diffusion layer. The second diffusion layer is coupled only to the common contact.

Semiconductor device with common contact coupling gate wiring integrated with gate electrode of antifuse to diffusion layer

A semiconductor memory device includes a first insulating film provided on a semiconductor substrate between first and second diffusion regions, a first gate electrode provided on the first insulating film, a second insulating film provided on the semiconductor substrate between the second diffusion region and a third diffusion region, and a second gate electrode provided on the second insulating film. The first and second diffusion regions, first insulating film, and first gate electrode constitute a first memory cell, while the second and third diffusion regions, second insulating film, and second gate electrode constitute a second memory cell. The first and second gate electrodes are connected in common to form a word line electrode. The first and third diffusion regions are connected to first and second read bit lines. The second diffusion region is connected to a program and erase bit line.

Semiconductor memory device and control method and manufacturing method thereof

A semiconductor memory device is provided, which makes it possible to increase the capacitance of capacitors in the capacitor section without degrading the withstand voltage of the capacitor dielectric. This device comprises a memory cell section including floating-gate type transistors and a capacitor section including capacitors. The memory cell section and the capacitor section are formed on a semiconductor substrate. Each of the transistors has a first gate dielectric, a floating gate, a second gate dielectric, and a control gate. Each of the capacitors has a lower electrode, a capacitor dielectric, and an upper electrode. A first part of the capacitors is/are designed to be applied with a first voltage and a second part thereof is/are applied with a second voltage on operation, where the first voltage is lower than the second voltage. Each of the first part of the capacitors has a recess formed on the lower electrode, thereby increasing its capacitance.

Semiconductor memory device and method of fabricating the same

The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lover erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole. However, when only some memory cells of a group have a higher erase speed, an excessive erase requiring electric charge supply occurs only in some memories and accordingly, it is possible to rapidly complete the data.

Semiconductor storage device and production method thereof

A semiconductor memory device is provided, which makes it possible to increase the capacitance of capacitors in the capacitor section without degrading the withstand voltage of the capacitor dielectric. This device comprises a memory cell section including floating-gate type transistors and a capacitor section including capacitors. The memory cell section and the capacitor section are formed on a semiconductor substrate. Each of the transistors has a first gate dielectric, a floating gate, a second gage dielectric, and a control gate. Each of the capacitors has a lower electrode, a capacitor dielectric, and an upper electrode. A first part of the capacitors is/are designed to be applied with a first voltage and a second part thereof is/are applied with a second voltage on operation, where the first voltage is lower than the second voltage. Each of the first part of the capacitors has a recess formed on the lower electrode, thereby increasing its capacitance.

The present invention prevents a charge-up during a wiring layer etching in a nonvolatile semiconductor storage apparatus, having a floating gate and a control gate to which both of positive and negative voltages are applied during a memory cell operation, by providing a current path from the control gate to a substrate via a charge-up preventing element. A first well is formed in the substrate. A second well is formed in the first well. The charge-up preventing element is formed in the second well. The substrate and second well are of one conductive type (p or n) and the first well and charge-up preventing element are of the other conductive type. Before memory cell operation, the control gate is disconnected from the charge-up preventing element.

Nonvolatile semiconductor storage apparatus and production method of the same

The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lower erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole.

There is provided a semiconductor memory device including a semiconductor substrate, a floating gate type transistor formed on the semiconductor substrate, acting as a memory cell of the semiconductor memory device, and a charge pump circuit formed on the semiconductor substrate. The transistor includes (a) a first gate insulating film formed on the semiconductor substrate, (b) a floating gate electrode formed on the first gate insulating film, (c) a second gate insulating film formed on the floating gate electrode, and (d) a control gate electrode formed on the second gate insulating film. The charge pump circuit includes (a) a plurality of diode devices formed on a third insulating layer formed on the semiconductor substrate, and electrically connected with each other in series, and (b) a plurality of capacitors each of which is electrically connected to a terminal of each of the diode devices. The above mentioned semiconductor memory device significantly reduces a parasitic capacity to thereby enhance a step-up efficiency. Thus, it is possible to reduce power consumption in a charge pump circuit and further reduce a total area required for a semiconductor memory device.

The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lower erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole. However, when only some memory cells of a group have a higher erase speed, an excessive erase requiring electric charge supply occurs only in some memories and accordingly, it is possible to rapidly complete the data erase in the memory cells of the group.

A nonvolatile semiconductor memory device and a method of fabricating the device are provided that allow the use of dry etching when removing the ONO film and that eliminate the danger of etching the silicon substrate in the gate oxide film formation areas even in the event of over-etching. In the process of fabricating a nonvolatile semiconductor memory device that is provided with a memory cell area including nonvolatile memory and a peripheral circuit area including circuits for controlling the nonvolatile memory, an insulative material that is to become an insulating film overlying floating gate electrodes is formed over the entire surface of each area and over a first conductive layer in the peripheral circuit area, and a dummy pattern is provided in the boundary areas between the memory cell area and peripheral circuit area so as to surround the memory cell area, this dummy pattern being composed of: a first conductive material that constitutes the floating gate electrodes of the nonvolatile memory, a second conductive material that constitutes the control gate electrodes of the nonvolatile memory, and an ONO film that constitutes an insulating film between the floating gate electrodes and the control gate electrodes.

Nonvolatile semiconductor memory device and fabrication method

A plurality of memory cells are arranged in lattice arrangement to form a memory cell array. Each of the memory cells is provided with a source. Data in the memory cell can be electrically written and erased. Sources of all the memory cells are connected in common. Also, a source voltage control circuit having two or more kinds of load characteristics is connected to the sources connected in common. According to a load characteristics selected from a plurality of load characteristics, source voltage of the memory cell is controlled.

Non-volatile semiconductor memory device

In a method for manufacturing a semiconductor memory device including a plurality of field areas, a plurality of electrode areas, a plurality of source areas and drain areas sunrounded by the field areas and the electrode areas, before forming field insulating layers for isolating the source and drain regions, impurities are introduced into the field areas between the source regions, to create an additional source region below the field insulating layer for isolating the source regions. The additional source regions are linked between the source regions.

Growing community of inventors

Tokyo, Japan

Kiyokazu Ishige