Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kiyohito Nishihara

Fumitaka Arai

Makoto Mizukami

Masaki Kondo

Atsushi Fukumoto

Masumi Saitoh

Kikuko Sugimae

Takayuki Ishikawa

Atsuhiro Sato

Shosuke Fujii

Takashi Izumida

Tadashi Iguchi

Yasuhiko Matsunaga

Fumiki Aiso

Makoto Sakuma

Hiroshi Akahori

Masato Endo

Shigeo Kondo

Daigo Ichinose

Hirokazu Ishida

Takashi Ichikawa

Hidenobu Nagashima

Kazuaki Iwasawa

Naohisa Iino

Keiji Shuto

Yingkang Zhang

A memory device according to one embodiment includes a resistance change film, an insulating film provided on the resistance change film, a first wiring provided on the insulating film and being not in contact with the resistance change film, and a high resistance film having a higher resistivity than the first wiring. The high resistance film is provided on a side surface of a stacked body including the insulating film and the first wiring, and the high resistance film is electrically connected between the first wiring and the resistance change film.

Memory device and method for manufacturing the same

A memory device includes a substrate, first and second wirings above the substrate, a third wiring above the first and second wirings, a fourth wiring above the third wiring, a first contact electrically connected between the first wiring and the fourth wiring, a first insulator on the first contact, and a second contact on the first insulator, the second contact being electrically connected between the second wiring and the third wiring. The first contact overlaps the second contact in a direction that is orthogonal to an upper surface of the substrate.

Memory device and manufacturing method thereof

According to an embodiment, a nonvolatile memory device includes: a first interconnection layer extending in a first direction; a second interconnection layer extending in a second direction crossing the first direction, the second interconnection layer including a metal-containing layer and a metal ion source layer, and the metal ion source layer being provided on the first interconnection layer side; and a resistance change layer provided in a position where the first interconnection layer and the second interconnection layer cross each other and a metal ion released from the metal ion source layer being capable to be diffused into the resistance change layer. At least part of the second interconnection layer protrudes to the first interconnection layer side in a cross section of the second interconnection layer cut perpendicularly to the second direction.

Non-volatile memory device

A memory device according to an embodiment, includes a substrate, two or more resistance change memory cells stacked on the substrate, two or more transistors stacked on the substrate, and two or more wirings stacked on the substrate. One of the memory cells and one of the transistors are connected to each other via one of the wirings.

Memory device

According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of element-separating insulators, and contacts. The plurality of element-separating insulators partition the upper layer portion into a plurality of active areas extending in a first direction. The contacts are connected to the active areas. A recess is made in a part in the first direction of an upper surface of each of the active areas. The recess is made across the entire active area in a second direction orthogonal to the first direction. Positions in the first direction of two of the contacts connected respectively to mutually-adjacent active areas are different from each other. One of the contacts is in contact with a side surface of the recess and not in contact with a bottom surface of the recess.

NAND type nonvolatile semiconductor memory device and method for manufacturing same

A nonvolatile memory according to an embodiment includes a first wiring line; a second wiring line arranged above the first wiring line and extending in a direction crossing the first wiring line; and a resistance change layer arranged in an intersection region of the first wiring line the second wiring line, the second wiring line including a first member extending in the direction in which the second wiring line extends, and an electrode layer containing a metal element arranged on a side surface of the first member along the direction in which the second wiring line extends, a lower surface of the electrode layer being in contact with an upper surface of the resistance change layer.

Nonvolatile memory

According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film.

Nonvolatile memory device

A semiconductor device according to an embodiment of the present invention includes a substrate, isolation layers and active regions formed in the substrate, and arranged alternately along a first direction parallel to a surface of the substrate, an inter layer dielectric formed on the isolation layers and the active regions, and having holes for respective contact plugs on the respective active regions, barrier layers formed in the holes, each of the barrier layers being formed on a top surface of an active region exposed in a hole and on one of two side surfaces of the hole, the two side surfaces of the hole being perpendicular to the first direction, and plug material layers formed on the barrier layers in the holes.

Semiconductor device and method of manufacturing the same

According to one embodiment, a nonvolatile semiconductor memory device includes: a semiconductor substrate; an element isolation insulator formed in an upper portion of the semiconductor substrate and dividing the upper portion into first and second active areas extending in a first direction; a first contact connected to the first active area; and a second contact connected to the second active area. Each of the first and second active area includes: a first portion connected to one of the first contact and the second contact; and a second portion having an upper surface being placed lower than an upper surface of the first portion. The first contact and the second contact are mutually shifted in the first direction. The first portion of the first active area is disposed adjacent to the second portion of the second active area.

Nonvolatile semiconductor memory device

Two diffusion layers are provided in an element area. A tunnel insulating film is provided on the surface of the element area between the two diffusion layers. A charge storage layer is provided on the tunnel insulating film. A first insulator provided on the upper surface of the charge storage layer. An inter-electrode insulating film provided on the first insulator, on the side surface of the charge storage layer in a first direction and on the isolation insulating film. And a control gate electrode extends in the first direction and covers the charge storage layer via the first insulator and the inter-electrode insulating film. The first insulator is thicker than the inter-electrode insulating film, and the inter-electrode insulating film has a first slit on the first insulator.

Nonvolatile semiconductor flash memory

A semiconductor memory device includes a substrate having a step including a first upper surface and a second upper surface higher than the first upper surface, a memory cell array formed on the first upper surface, and a peripheral circuit formed on the second upper surface and configured to supply an electrical signal to the memory cell array. The memory cell array includes a stacked structure having a plurality of first interconnection layers and a plurality of second interconnection layers respectively connected to the first interconnection layers. The first interconnection layers are stacked on the first upper surface, are separated from each other by insulating films, and extend in a first direction. The second interconnection layers extend upward and are separated from each other by insulating films.

Semiconductor memory device

A write and erase method of a semiconductor memory device includes a floating gate type transistor having a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, and a control gate electrode opposing the floating gate electrode with a hollow portion being sandwiched therebetween. A capacitance between the semiconductor substrate and the control gate electrode is controlled by one of an operation of forming, in the hollow portion, an electrical path which electrically connects the floating gate electrode and the control gate electrode, and an operation of eliminating the electrical path.

Semiconductor memory device and write method of the same

A first lamination part includes: a charge accumulation layer provided on the respective sidewalls of laminated first conductive layers and accumulating charges; and a first semiconductor layer provided in contact with the fourth insulation layer and formed to extend to the lamination direction. A second lamination part includes a second semiconductor layer provided in contact with the first semiconductor layer. A third lamination part includes: a plurality of first contact layers formed in contact with the respective second lamination part, extending to a first direction perpendicular to the lamination direction, and in line with each other along a second direction perpendicular to the first direction; and a plurality of contact plug layers formed in contact with any one of the first contact layers and extending to the lamination direction. The contact plug layers are arranged at different positions relative to each other in the first direction.

Non-volatile semiconductor storage device and method of manufacturing the same

A depletion-type NAND flash memory includes a NAND string composed of a plurality of serially connected FETs, a control circuit which controls gate potentials of the plurality of FETs in a read operation, a particular potential storage, and an adjacent memory cell threshold storage, wherein each of the plurality of FETs is a transistor whose threshold changes in accordance with a charge quantity in a charge accumulation layer, the adjacent memory cell threshold storage stores a threshold of a source line side FET adjacent to a source line side of a selected FET, and the control circuit applies a potential to the gate electrode of the source line side FET in the read operation, the applied potential being obtained by adding a particular potential stored in the particular potential storage to a threshold stored in the adjacent memory cell threshold storage.

Depletion-type NAND flash memory

A semiconductor memory device comprises a semiconductor memory, a corrected voltage storage circuit which stores a corrected voltage produced by correcting a read voltage of the semiconductor memory, and a memory controller which reads the corrected voltage from the corrected voltage storage circuit and performs a read operation of the semiconductor memory using the corrected voltage.

Growing community of inventors

Yokohama, Japan

Kiyohito Nishihara