Tokyo Electron Limited

Kiyohito Iljima

Seiichi Kaise

Akira Obi

Keiko Takahashi

At a time Tp when a wafer W is transferred into either a load lock chamber LLor LL, periods PSL for the load lock chambers LLand LLto get ready to permit a transfer of a next wafer W thereinto are calculated based on a timing for exchange of wafers W between the load lock chamber LLor LLand a loader module LM. When the periods PSL are calculated, a loader arm LAor LAselects a next wafer W having the shortest period to get ready to be transferable into the load lock chamber LLor LL, from load ports LPto LP. This improves transfer delay in a cluster tool provided with the load lock chambers.

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Nirasaki, Japan

Kiyohito Iljima