Renesas Electronics Corporation

Other

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Kiwamu Takada

Osamu Nishii

Kunio Uchiyama

Masayuki Miyazaki

Masaru Kokubo

Hirokazu Aoki

Kiyoshi Hasegawa

Ken Tatezawa

Yoichi Yuyama

Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core and the second CPU core respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnosed result.

Lockstepped CPU selection based on failure status

In a data processing device including two sets of circuit pairs which are respectively duplicated in two clock domains which are asynchronous to each other, an asynchronous transfer circuit that transfers a payload signal is provided between the two sets of circuit pairs. The asynchronous transfer circuit includes two sets of a pair of bridge circuits which are respectively connected to the two sets of circuit pairs, and asynchronously transfers the payload signal and a control signal indicating a timing at which the payload signal is stable on a reception side. The two sets of a pair of bridge circuits and the payload signals can be duplicated, but the control signal is not duplicated, and the received payload signal is used for timing control to supply an expected same time difference, to the pair of duplicated circuits. This enables asynchronous transfer between circuits duplicated in the asynchronous clock domains.

Data processing device

Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core and the second CPU core respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnose result.

Semiconductor device with output data selection of lockstepped computing elements based on diagnostic information

A semiconductor integrated circuit device employing two clock signal generating circuits which output clock signals for distribution to an internal circuit of the device, the first and second clock signal generating circuits having different clock-settling times and the selection thereof is effected from outside of the device. A first one of the clock signal generating circuits uses, for example, a phase-locked loop circuit which has a large clock-settling time, and the second clock signal generating circuit is implemented, for example, using a delay-locked loop circuit whose clock-settling time is small, for example, 2-3 periods. Due to the selective actuation of the second clock signal generating circuit, which has a small clock-settling time, the generating of clock signals for the internal circuits can also be halted when the internal circuits of the device are halted thereby to further lower power consumption without compromising clock oscillator responsiveness.

Semiconductor integrated circuit device

A signal from a crystal resonator or an external clock signal are input from terminals xta or exta and the signal from the crystal resonator or external clock signal are selected by mode terminal mod and input to an oscillator OSC. An input clock signal ckl is frequency-divided to desired values by a divider DIV A divided clock signal clk is input as the reference clock of a phase-locked loop PLL or delay-locked loop DLL and a clock signal output by a circuit selected by a selector SEL passes via a divider DIV to be distributed to an LSI. The phase-locked loop PLL has a clock settling time of at least 40 clock periods, whereas the clock settling time of the delay-locked loop DLL is 2-3 periods.

Growing community of inventors

Kanagawa, Japan

Kiwamu Takada