Hewlett-packard Company

Agilent Technologies, Inc.

Kit M Cham

Eric Y Chou

Robert E Gleason

Paul V Voorde

Frederick A Perner

Shawming Ma

Jeremy Alfred Theil

Ye Chen

Dietrich Werner Vook

Min Cao

Christopher L Coleman

Ronald T Kaneshiro

Gary William Ray

James Joseph Dudley

Myunghee Lee

Stefano G Therisod

Wayne M Greene

Xin Sun

Craig T Cummings

Jane M J Lin

Steven A Lupi

Jane M Lin

Yu-Chun Chang

For each channel in a parallel channel optical array, a diffractive optical arrangement (DOA) includes an input region that is configured to pass a first portion of an input beam to an output region for data transmissions and to diffract and direct a second portion to a detection region for monitoring. The input region includes the diffractive features of a computer generated hologram (CGH) or a grating for diffracting. Alternatively, the input region is coupled to the CGH or grating. Moreover, the DOA includes at least one reflective region for redirecting the second portion. In one embodiment, the DOA includes a separate active surface for each channel of the array. Alternatively, the DOA has a singular active surface that is positioned to interact with all the channels. Optical power output from the second portion is monitored to generate feedback signals for adjusting the input current to each laser. Additionally, optical power output from sensed temperature is monitored to generate feedback signals.

Integrated parallel channel optical monitoring for parallel optics transmitter

An active pixel sensor. The active pixel sensor includes a photo-diode. The photo-diode conducting charge as a function of the intensity of light received by the photo-diode. The photo-diode includes a diode capacitance which collects charge conducted by the photo-diode which generates a photo-diode voltage. A switched capacitor is connected in parallel with the photo-diode when the photo-diode voltage drops below a pre-determined voltage potential. A capacitance of the switched capacitor adds to the diode capacitance when the switched capacitor is connected. The switched capacitor can be a gate capacitor. The active pixel sensor further includes electronic circuitry to allow a controller to sample the photo-diode voltage.

Adjustable gain active pixel sensor

An active pixel sensor. The active pixel sensor includes a substrate, an interconnect structure adjacent to the substrate, and at least one photo sensor adjacent to the interconnect structure. At least one photo sensor is formed adjacent to the interconnect structure. Each photo sensor includes a pixel electrode which includes a patterned doped semiconductor layer. An I-layer is formed adjacent to the patterned doped semiconductor layer. A transparent electrode is formed adjacent to the I-layer. A method of forming the active pixel sensor includes forming an interconnect structure over a substrate. Next, a doped semiconductor layer is deposited over the interconnect structure. The doped semiconductor layer is etched forming pixel electrode. An I-layer is deposited over the pixel electrodes. Finally, a transparent conductive layer is deposited over the I-layer.

Elevated pin diode active pixel sensor which includes a patterned doped

A salient integration mode active pixel sensor. The active pixel sensor includes an amplify/compare transistor which has a threshold voltage. The amplify/compare transistor couples an input of the amplify/compare transistor to an output of the amplify/compare transistor when the input of the amplify/compare transistor exceeds the threshold voltage. A photo-diode generates a signal voltage which has a voltage level dependent upon the intensity of light received by the photo-diode. The signal voltage is coupled to the input of the amplify/compare transistor. A reset element couples a reset line to the photo-diode and discharges the photo-diode when the reset line is active. A coupling capacitor for couples a select line to the input of the amplify/compare transistor. The select line causes the input to the amplify/compare transistor to exceed the threshold voltage and thereby couple the signal voltage to the output of the amplify/compare transistor. The amplify/compare transistor can be an N-type MOSFET and the reset transistor can be an N-type MOSFET. Further, a back gate of the amplify/compare transistor is generally connected to a circuit ground.

Salient integration mode active pixel sensor

A novel BICMOS output buffer is taught including circuit means for firstly discharging the bases of the bipolar pull up and bipolar pull down transistors, and secondly to connect the base of an output transistor to its emitter when that output transistor is conducting, thereby insuring maximum voltage swing of the output voltage. The circuit means comprises an MOS transistor for discharging the base of an output transistor, and a depletion mode MOS transistor for connecting the base of an output transistor to its emitter. By utilizing MOS and depletion mode transistors, a significant area advantage is achieved, particularly when the MOS and depletion mode transistors are merged.

BICMOS logic gate circuit and structures

BICMOS logic gate with higher pull-up voltage

A MOSFET structure characterized by a lightly doped tip region located between the channel and drain, and a buried region located below the tip region and shifted laterally towards the drain. The buried region, which is doped to a level intermediate between that of the tip region and the drain, causes the channel current to deflect downwardly from the field oxide, through the lightly doped tip region, and into the buried region. The gradual electric field gradient produced by the structure and the deflection of the channel current away from the thin oxide greatly reduces the device's sensitivity to the hot electron effect. The method of the invention includes forming the lightly doped tip region, forming a first oxide spacer, forming the buried region, widening the oxide spacer, and finally forming the drain region.

MOSFET structure and method for making same

Method for making an LDD MOSFET with a shifted buried layer and a

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Cupertino, CA, United States of America

Kit M Cham